Honored Contributor
Honored Contributori had the same problems with the sdram controller. and as the result i wrote my own controller which runs at 125 mhz on ep1c12 with speed grade 8.
i tested it with nios core at 75 mhz + video generation unit as an 8 words burst read master.
video unit runs at two clocks - 24mhz and avalon interface block works at the same speed as sdram. so you can see that all synchronisations of clk were done inside my component, not with avalon bus. furthermore this double master system works perfectly.
still the core needs testing, therefore i send it to mschmitt and i hope to post it at opencores.org soon.
it would be great if you join me.
ps. remember it's just the begining of the project and i haven't written any documentation, just basic comments inside source code.
good luck!
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--- Quote End --- Hi NTPQA, what about your SDRAM Core? I'm very interested in that. Could i get the Core for testing? Thanx Marco
