Forum Discussion
Altera_Forum
Honored Contributor
19 years agoJust the same issue here, trying to get the other masters to keep up to the speed of the SDRAM, just to prevent the penalty (or the problems) with the clock domain crossing.
That is the reason why I want to try the Microtronix SDRAM controller, but some adjustments must been made by them (I'm waiting....). I have a lot of confidence in this controller, because it should have two independed slaves, that access the same memory. So I hope to connect my NIOS to one slave, my other (slower masters) to the other. And because the SDRAM controller itself runs at a faster speed, it should be possible to serve both interfaces. Of course there is the same penalty then for the clock domain crossing, but I plan to use an asynchronuous RAM to store the fast part of the program/data. I let you know when I have tried. Stefaan