Forum Discussion
Altera_Forum
Honored Contributor
19 years agoThanks for your comments about this topic.
I did also thought about running the sdram at a higher clock speed than the nios. The sdram used is a micron type and should run up to 133MHz. My external clock is 48MHz so i could tune the SDRAM up to 128MHz (8:3setting) and the nios with all other modules runs at 64MHz. This means the sdram has twice the speed than the nios, but taking into account that i get 6 clock penalty from the clock crossing domain the nios would run at 1/3 the speed it runs now. well i am not shure if 1/3 of nios execution speed is the problem if i could get the other masters to access the sdram within the max available clocks each masters for its access. but if i tune sdram to twice the speed of all other modules does this mean that i get the clock penalty of 6 clocks for each master ? does this slow down the whole stuff instead of speeding it up ? Michael Schmitt