SDRam Controller is there a better one ?

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originally posted by mschmitt@Sep 1 2006, 07:20 AM

maybe somebody has a recomendation for me ...

i use the sdram controller that is part of the sopc builder.

the external sdram is 2 chips each 16 bit wide.

inside the fpga cycloneii there are several avalon masters.

niosii, 100mbit ethernet mac and some custom avalon masters.

currently i have a minimum of 7 avalon masters eqach accessing the sdram.

now it is abvious that the sdram is the bottle neck.

4 of the custom avalon masters needs to read or write 32bit from or to the sdram each 160 clocks. but the avalon switch fabric assert a waitrequest for a read of up to 60 clocks cycles. so 4 of these avalon masters could lead to an access problem.

has anybody a recomendation of a different sdram controller ?

out of my head i think i remember that the sdram controller that is part of the sopc builder was called "poor" and that there are better ones.

the avalon switch fabric i capable of setting some arbitrations.

i gave my own sopc modules higher numbers (2) than the nios2 (1) or the ethernet mac.

any recomendations how to speed up the sdram access ? fclock ist 64mhz. and quartus seems to have problems with incrementing fclk and fitting.

michael schmitt

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You say "I use the sdram controller that is part of the sopc builder". Are you talking about the SDRAM v3.4.0 DDR/DDR2 Altera SDRAM Megacore IP ?

BR