Forum Discussion
Occasional Contributorqspi driver in NIOS bsp in Cyclone 10
Hi,
I am running NIOS II in Cyclone 10 LP 10CL120YF484.
The flash I am using is M25P64 which is qspi interface.
The problem is that EPCS flash controller is not compatible for Cyclone 10.
I am going to run qspi flash driver in NIOS so that I can read and write the flash.
The question is:
is qspi friver available? Could you please tell me the related resource of qspi driver and API?
23 Replies
Archer_AlteraHi Zhiqiang,
You may use Quartus version 20.1 Standard or later version. Then you can find GSFI IP in Platform Designer tool and refer to document description in link below to implement the booting from GSFI flash solution.
On page 8, it describes how to change the example driver to match the device from other flash vendor.
Hope it is helpful.
ZhiqiangLiangThank you for your reply!
This question is very critical for my design.Is there a way by which I can run the GSFI IP on Quartus 18.1?
- Archer_Altera
Hi Zhiqiang,
I look at quartus 18.1std tool, it has GSFI IP too. Please try it.
The example design in quick start guide document is created in quartus 18.1std.1. So quartus 18.1std.1 should be OK to use this IP.
Cyclone® V FPGA – Generic Serial Flash Interface and Nios® II Processor Booting Design Example
If you are OK to upgrade to 18.1std.1 version, you may go to Intel® Quartus® Prime Standard Edition Design Software Version 18.1 for Windows and download update 1 setup package shown as below.
Hope this is helpful.
- ZhiqiangLiang
Thank you!
I have already found a good IP(Serial Flash Controller Intel FPGA IP) that supports EPCS64 flash.
I have already tried this IP. I can program jic file via Quartus--> Tools--> Programmer.
but I can't program elf file via Eclipse--> NIOS II --> Flash Programmer.
Is there any way to program elf file or binary of C code if I use Serial Flash Controller Intel FPGA IP?
- Archer_Altera
Hi Zhiqiang,
Please refer to ug_nios2_flash_programmer document in link below, it provides the method of programming SOF and ELF file into EPCS flash.
https://cdrdv2.intel.com/v1/dl/getContent/666773?explicitVersion=true
Hope this is helpful.
- ZhiqiangLiang
Thank you!
I have already read the pdf you mentioned. The picture I pasted is the result when I follow the pdf.
- Archer_Altera
Hi Zhiqiang,
Below table shows the minimum component set required. Have you enabled JTAG debug module level1 or greater?
- ZhiqiangLiang
- Archer_Altera
Hi Zhiqiang,
It is set in Nios II processor IP shown as below.
- ZhiqiangLiang
Thank you!
By default, Platform Designer set JTAG Debug mode. I have never set or changed it.
Let's go back to my question:
I followed the settings in your link pasted above, but I am still facing the issue that NIOS II Flash Programmer can't find the device.
Could you please tell me how to solve that issue?
If it is possible, could you please contact me by me personal email: [email protected]
- Archer_Altera
Hi Zhiqiang,
Since you can download JIC file, one possible solution is to convert elf file into hex file, and then add hex file into JIC file.
There are detailed online descriptions for your reference as below.
https://www.intel.com/content/www/us/en/support/programmable/articles/000076639.html
- ZhiqiangLiang
Thank you！
If I convert elf into hex file according to your link, the questions are:1) how to specify the start flash address of hex data?
2) how does NIOS know the start flash address of hex data?
3) will any component copy hex data from flash to RAM when NIOS boots?
- Archer_Altera
Hi Zhiqiang,
Please refer to below document and go through the description related to EPCS.
- ZhiqiangLiang
Thank you!
I read the description related to EPCS in your link which is really helpful.
There are 3 steps to generate elf image hex file:sof2flash --input= TFT_SRAM.sof --output=hwimage.flash --epcs –verbose
elf2flash --input=tft_touch.elf --output=swimage.flash --epcs --after=hwimage.flash –verbose
nios2-elf-objcopy --input-target srec --output-target ihex swimage.flash swimage.hexmy questions are:1) My flash is EPCS64, in the upper commends, should I use --epce64 or --epcs?2) If I follow your link to program jic file, I don't need to generate ROM in Platform Designer, right? I should remove the ROM in the design in the following picture, right?After I remove ROM in my design, I add "Serial Flash Controller Intel FPGA IP".I set NIOS II reset vector memory in the following picture."Serial Flash Controller Intel FPGA IP " is connected to NIOS II shown in the following picture.3) when I run sof2flash command, I encountered the issue:May 28, 2025 2:53:38 PM - (FINE) sof2flash: Starting
foo:10A10CL120YF484I7GMay 28, 2025 2:53:38 PM - (SEVERE) sof2flash: Unrecognized device family in SOF.
The sof2flash utility takes an FPGA configuration file in SOF format and
translates it to a FLASH file that can be programmed into the flash
memory connected to an Altera FPGA.The device model I am using is: Cyclone 10 LP 10CL120YF484.4) I follow the steps blow :quartus_cpf -c --device=EPCS64 -o auto_create_rpd=on -o rpd_little_endian=on NIOS_BF5V.sof NIOS_ONLY_sof.pof
nios2-elf-objcopy -I binary -O srec --srec-forceS3 --srec-len 32 NIOS_ONLY_sof_auto.rpd NIOS_ONLY_sof.flash
nios2-elf-objcopy -I srec -O ihex NIOS_ONLY_sof.flash hwimage.hex
elf2flash --input=BF5V_C.elf --output=swimage.flash --epcs --after=NIOS_ONLY_sof.flash --verbose
nios2-elf-objcopy -I srec -O ihex swimage.flash swimage.hexI can generate the hex file. however, when I do Eclipse-->Run-->Run Configurations and Run, Eclipse report the following error.- Archer_Altera
Hi Zhiqiang,
The steps in item 4 as you described are the right solution to solve unrecognized SOF issue when run SOF2FLASH command.
Now you can generate hex file. Have you tried to add it into JIC file and program into flash as described in link below? Can your system boot from epcs flash now?
https://www.cnblogs.com/xiaomeige/p/6709991.html
About error when you try Eclipse-->Run-->Run Configurations and Run, please kindly create a new case for it. Thank you for your cooperation.
- ZhiqiangLiang
Thank you!
After I generate sw hex file, I add it to Convert Programming File tool with sof file, and generate jic file and then burn it to flash with Quartus-->Tools--> Programmer tools. The programming is reported successfully.
when I generate hex file, I cannot understand those parameters, could you please help to explain them? or paste the link about the explanation of those parameters? For example, what is auto_create_rpd? why is it on? what is it for? what is rpd_little_endian? why is it on?
what is srec-forceS3? what is srec-len?
After the upper programming, I don't know whether the SW(C code ) could be run in NIOS(FPGA) as I cannot debug it from Eclipse. The reason is pasted in my upper post.
Please see the third picture in my upper post. Eclipse report: Verify failed between address 0x1000000 and 0x100FFFF.
I doubt there is a mistake in my operations. when I generate jic file, there is a map file generated. please the the map file below pasted.
My doubt is:
swimage start address in flash is: 0x00367F06, why did Eclipse very the address 0x1000000 and 0x100FFFF?
where and how can I tell Eclipse the sw image start address?
BLOCK START ADDRESS END ADDRESS
Page_0 0x00000000 0x00367F05
swimage.hex 0x00367F06 0x00380875
Configuration device: 10CL120Y
Configuration mode: Active Serial
Quad-Serial configuration device dummy clock cycle: 8
Notes:- Data checksum for this conversion is 0x49A89CF7
- All the addresses in this file are byte addresses
SueC_AlteraContributor
Hi ZhiqiangLiang,
Your original question has been answered. For the follow on question, please start a new thread.
If you are looking for term definitions, please use Google or some other search engine to find definitions.
Thanks,
Sue
