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Altera_Forum's avatar
Altera_Forum
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15 years ago

Porting PIO C-code from ARM-7 to Nios II (SE1-board) + performance issue.

Hi all,

I'm having a try at the moment to port my C-code from the arm-7 mcu, LPC-P2148 to Nios II, SE1-board , Cyclon-II, EP2C20F484C7. The arm-none-eabi-gcc compiler was used for the ARM-7 MCU and the NIOSII Eclipse Platform , version 9.1 for the nios ii/e cpu. ( e CPU: Cost and licence is based ). More details can bei obtained from my homepage.

A) Performance issue:

ARM-7: 12MHz clock , running at 48 Mhz via PLL.

Nios II/e 50MHz clock , running at 50 Mhz.

Used code: ( shifting LED Demo )

void startup_leds(void);

void delay(void);# include <stdio.h># include <system.h># include "altera_avalon_pio_regs.h"

//

void startup_leds(void)

{

short is;

short count = 4;

int laufled = 0x00000001;

for (count = 0; count < 4; count++ ) {

for (is = 0; is < 16; is++ ) {

IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, laufled);

// IOPIN1 = laufled<<16; // was ARM-Code

delay(); // wait

laufled = laufled <<1;

}

for (is = 0; is < 16; is++ ) {

//IOPIN1 = laufled<<16; // was ARM-Code

IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, laufled);

delay(); // wait

laufled = laufled >>1;

}

}

}

//

void delay(void)

{

short int wait = 6000; // arm-7: 50000 for same speed.

while (wait) {

wait = wait -1;

}

}

//

int main(void)

{

short count = 0;

int delay;

printf(" Hello from Nios II \n\r");

startup_leds();

while(1)

{

startup_leds();

}

return 0;

}

Result. the arm-7 runs about 7 times faster than the nios ii/e !

Is the reason based on the Nios II/e CPU ?

Maybe something wrong configured via SOPC Builder?

Is my C-code correct?

IOPIN1 = laufled<<16; = ARM-7 code with additional 16 ASR !

Converted to : OWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, laufled);

B) What is the recommendation reading Data from a PIO or test

the condition from a single bits. For Example, I want to check the

status of BIT-16. The ARM-7 C-code Statement

if (!( IOPIN0 & 0x00010000 )) .... Nios II statement ?

I was playing around with the IORDALTERA_AVALON_PIO_DATA(base)

but without any success yet.

Problem with SOPC Builder and PIO optional settings ?

Everybody answer is welcome, Regards , Reinhard

29 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Check the compiler options - especially for -O2 or -O3.

    And check that your delay loop doesn't get optimised away!

    An asm volatile("\n":::"memory") inside the loop should persuade gcc to generate all the code.

    Oh - and, in general, don't use 'short int' unless you are trying to pack data into a structure or require the compiler to generate code that explicitly wraps on the small boundary.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Nios II/e has a MIPS/Mhz ratio from 0.105 to 0.15 depending on the fpga device family. An ARM7 core has a MIPS/Mhz ratio of nearly 1. This is about 7 times the performance a Nios II/e has. Nios II/e does not have a pipeline, this makes the instruction execution of this core slow.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Many thanks for the upgrade info although the answer is not good for me because I need at least the performance of an ARM-7. Do you think a Nios II/s or Nios II/f CPU is able to perform like a ARM-7 CPU ? Also, as far as I know, these Nios II CPU's are only useable with a special licence ? Too bad for me and it looks to me to redesign my project completely.

    Concerning question B): This "problem" is fixed, I configured via SOPC Builder a PIO with extra input and output channel. The ported Statemant:

    if (!( IORD_ALTERA_AVALON_PIO_DATA(PIO_0_BASE) & 0x00010000 ))

    is now working fine ( only to slow :confused: )

    Many thanks and regards.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    The other Nios cores are definitely faster, but I don't think they reach a 1 MIPS/MHz ratio though.

    You can evaluate them without paying, the only thing is that you won't be able to write the design to flash, and will need to keep the USB connection on while you run your application.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    If you are careful, and are executing code from tightly coupled memory, it is possible to avoid almost all pipeline stalls. This will give you one instruction per clock.

    You will need to inspect the generated code though, and modify the source in places (mainly to avoid register spills, stalls due to 'late result' on memory reads and mispredicted branches).
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Why not adding a cache between NiosII-e and the external memory ?

    Reinhard, your NiosII-e runs @ 50MHZ as well as your SDRam.

    By placing a cache between NiosII-e and SDRam this could speed up your execution.

    Such a cache (with wishbone interface) is used by the zet project and available as verilog soure. maybe it is time to write a wrapper around it that it acts as a slave to NiosII but and as a Master to SDramIP Controller ...

    This verilog source can be parametrized in deep and size
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    IMHO a cache does not signicantly improve the NIOS II/e performance. I think the 0.15 MIPS/MHZ are the best case achievable. A slow memory/memory interface worsens this value. NIOS II/e does not have a pipeline so instructions are executed one after another. An instruction has several stages, so the execution of one instruction lasts several clock cycles even if the attached memory can be accessed in one clock cycle. A fast memory/cache can reduce the length of the code fetch stage or the write back stage to a minimum, but it will still last several clock cycles before the next instruction is fetched.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    correct.

    but the cache could help, 512bytes is 1 M4K memory block so a few KB cache can help

    also Nios, cache SDRam could run at a higher clock rate whereas timer and others are placed in a slower clock domain.

    but what helps most is to get the timing relevant stuff into pure hardware
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    IMHO a cache does not significantly improve the NIOS II/e performance.

    --- Quote End ---

    Run a real program with instruction/data caches on and off and see for yourself that it makes a substantial difference. I tried to turn off caches (code and data) in 3 combinations to free up onchip RAM and the resulting speed was unusable for us.

    Bill A
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    disabling cache is only possible for NiosII-s or NiosII-f

    disabling the cache on one of them doesn't turn them into an equal NiosII-e

    The instruction execution is still faster than compared with an NiosII-e