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Altera_Forum
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15 years ago

Porting PIO C-code from ARM-7 to Nios II (SE1-board) + performance issue.

Hi all, I'm having a try at the moment to port my C-code from the arm-7 mcu, LPC-P2148 to Nios II, SE1-board , Cyclon-II, EP2C20F484C7. The arm-none-eabi-gcc compiler was used for the ARM-7 ...
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Altera_Forum
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15 years ago

correct.

but the cache could help, 512bytes is 1 M4K memory block so a few KB cache can help

also Nios, cache SDRam could run at a higher clock rate whereas timer and others are placed in a slower clock domain.

but what helps most is to get the timing relevant stuff into pure hardware