Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

OnChip memory access with external logic

Hi,

I'm trying to access on-chip memory (data and instruction) from external logic.

I've generated system with two dual ports on-chip memories one for data and one for instruction, and connected one port to the cpu and one port to Avalon master and ported this outside.

direct master - slave connection!

i can write and read from this memories.

a waitrequest signal is active in these connections - why?

and how can i remove it!.

this is reduce the BUS BW by factor 2 (at least)

and i want to use full BW.

thanks

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Probably your Avalon master interface needs to be a 'pipelined' master (I think that is what it is called), the internal memory ought to act as a pipelined slave.

    Another alternative is to have the external logic directly interface to the second port of the internal memory blocks. This is easiest if nothing else requires slave access to those areas (or you'll need to mux in requests from an Avalon slave).

    The nios cpu doesn't need read/write access to its code (except for booting from jtag etc), but you'll need to change the linker script to put readonly data in the data memory.

    If you are using gcc4 (as built by Altera) you have a bigger problem with the switch statement jump tables - which are always in .code. This can be fixed by rebuilding the compiler (see the wiki).
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Can you explain how to "directly interface to the second port of the internal memory blocks".

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Thinks ...

    This ought to be easy, but the SOPC builder's memory options probably only expose and avalon slave memory interface - whereas you need the raw signals for the 2nd port.

    There is also nothing defined to let you build your own 'tightly coupled memory' block (I've not looked - but I remember someone else saying it).
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Using Qsys you would be able to export one of the slave ports of the on-chip memory. That said the logic to create a direct connection is practically the same as creating an Avalon master so if it was me I would just build the master just in case you want more stuff to connect to the same memory which you can't do easily building up a direct connection.

    Like DSL said be sure to include the readdatavalid signal as well so that you can post back to back reads to the memory. You'll still want to throttle read/write access using the waitrequest signal, if your master is the only thing connected to the memory port and you make it a pipelined master then the waitrequest should never go active.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Thanks,

    i want to expose the memory ports, not the avalon slave - this i've done.

    in order to benefit a full BW usage of the memory.

    now i am using an simple avalon master, which utilize only half (even less) BW.

    i've defined new component with avalon master and export its signal. i didn't find the way to do so with pipeline master (only as bridge).

    i will try Qsys, i used SOPC.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    There is nothing special about the on-chip memory slave port, it directly wires up to the on-chip memory ports (generate one and take a look at the HDL to see for yourself). So whether you directly wire up to the on-chip memory port or the Avalon slave port doesn't matter since you are talking about wires at that point.

    If you use a simple master I would expect your peak memory efficiency on the reads to be 50% or 33% depending on whether you set the memory up for 1 or 2 clock cycles of latency. A pipelined master will hit a peak efficiency of 100%.

    Basically the master implementation is no different than wiring up some control logic to the slave. The only difference is the wait request and readdatavalid signals are needed to properly implement the master/hit high efficiency. It's extra work but it's trivial to implement and once you have those you can master any memory you want at that point.