OnChip memory access with external logic

There is nothing special about the on-chip memory slave port, it directly wires up to the on-chip memory ports (generate one and take a look at the HDL to see for yourself). So whether you directly wire up to the on-chip memory port or the Avalon slave port doesn't matter since you are talking about wires at that point.

If you use a simple master I would expect your peak memory efficiency on the reads to be 50% or 33% depending on whether you set the memory up for 1 or 2 clock cycles of latency. A pipelined master will hit a peak efficiency of 100%.

Basically the master implementation is no different than wiring up some control logic to the slave. The only difference is the wait request and readdatavalid signals are needed to properly implement the master/hit high efficiency. It's extra work but it's trivial to implement and once you have those you can master any memory you want at that point.