OnChip memory access with external logic

Probably your Avalon master interface needs to be a 'pipelined' master (I think that is what it is called), the internal memory ought to act as a pipelined slave.

Another alternative is to have the external logic directly interface to the second port of the internal memory blocks. This is easiest if nothing else requires slave access to those areas (or you'll need to mux in requests from an Avalon slave).

The nios cpu doesn't need read/write access to its code (except for booting from jtag etc), but you'll need to change the linker script to put readonly data in the data memory.

If you are using gcc4 (as built by Altera) you have a bigger problem with the switch statement jump tables - which are always in .code. This can be fixed by rebuilding the compiler (see the wiki).