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Altera_Forum
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Honored ContributorDownload But Verify Failed
Hi All,
I am using Nios Dev Board with MT48LC2M32B2 SDRAM(It is the only execute memory). When I make a software example and download it to sdram, it displays in nios IDE console: <div class='quotetop'>QUOTE </div> --- Quote Start --- Using cable "ByteBlasterII [LPT1]", device 1, instance 0x00 Pausing target processor: OK Reading System ID at address 0x02000880: verified Downloading 00800000 ( 0%) Downloaded 1KB in 0.0s Verifying 00800000 ( 0%) Verify failed Leaving target processor paused[/b] --- Quote End --- I find it is so popular problem with nios. Almost all designs using sdram will have the problem. Now, I only know that it has to do with Synchronization of sdram_clock and nios_system_clock, and can deal with the right phase shift value setting. But here I also have questions to ask about the problem. 1. About the verify failed problem, what's problem on earth? How many problems it should include? 2. I have sealed a new cyclone board with MT sdram, but I do not know clearly about how to set phase shift correctly in PLL setting. Can someone tell me how to alleviate clock skew between the SDRAM controller core and the SDRAM chip. 3. Can I simulate the timing in QUARTUS II of them? Or, can I use oscillograph(I use oscillograph, but can not observe)? I want the answer. Thank you, LiangYi12 Replies
Altera_ForumThere is an Altera provided document explaining the SDRAM core which also provides a calculation (at the very end) for the clock phase shift required:
sdram controller (http://www.altera.com/literature/hb/nios2/n2cpu_nii51005.pdf#) Hope that helps. I'm having the same problems and I'm trying various phase shifts...- Altera_Forum
Same here, a phase shift of -70 degrees was needed for correct behaviour
Good luck, Danny - Altera_Forum
One question I have is about the Altera calculation.
when it says take the lesser of the Read Lag or the Write Lag, there example has two positive numbers. Mine came out with a Read Lag of 5.95 ns, and a Write Lag of -0.267 ns. Now, do they literally mean the lesser of the two - meaning I would use the negative number (-0.267 ns)??? Anyone know? - Altera_Forum
Hi,
I have tested so many numbers, but all failed. So, I want to get a method that can deal with the problem easily. Furthre more, the phase shift is changed with frequency of the system, so we must have a method. Can Altera give us any information or application? Thank you, LiangYi - Altera_Forum
Did you check out the link to the datasheet that I provided? You tried lots of values, but did you try to calculate it with the Altera formulas?
- Altera_Forum
Hi,
I calculate the phase shift(in ns). First, I compile the whole system(include PLL but leave the phase shift '0'). Then, I get the Parameters about FPGA SDRAM I/O. F=50MHz tco_max=7.587ns, sdram_d22 tco_min=2.021ns, sdram_d1 th_max=-1.666ns, sdram_d1 tsu_max=2.183ns, sdram-d1 So, I get the value: -1.6745ns. But, it has the same problem. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif Altera do not make the document clearly, the values in the table indicate what on earth. LiangYi - Altera_Forum
I agree that the document could be better. For example, it doesn't tell you to negate (multiply by -1) the lesser of the Read/Write Lag - but in their example they did, so I assumed that I had to negate mine. It also doesn't say what to do if one or both numbers are negative (absolute value???!)
I can say though after recompiling my design and recalculating the phase shift, I came up with -2.3ns (which ends up being -90 degrees) and it seems to all be working now. - Altera_Forum
Hi lemonoje,
Can you paste you detailed implemention? You say <div class='quotetop'>QUOTE </div> --- Quote Start --- recompiling my design and recalculating the phase shift[/b] --- Quote End --- . I want to know how you get the right value from your recompiling design. Thank you, LiangYi - Altera_Forum
For my design:
clock = 100MHz ~ 10ns. Read Lag = toh(SDRAM)-thmax(FPGA) = 2.5ns-(-5.205ns) = 7.705ns Write Lag = tclk-tco_max(FPGA) - tds(SDRAM) = 10-4.325-2 = 3.675ns Read Lead = tco_min(FPGA) - tdh(SDRAM) = 2.65ns - 1ns = 1.65ns Write Lead = tclk - thz(3)(SDRAM) - tsu_max(FPGA) = 10ns-5.5ns-5.433ns = -0.933ns. Now it says take the lesser of each the lead and lag which would be -3.675 and -0.933. note that I negated the 3.675 which the Altera note deosn't tell you to do, but they did it in their example. the midpoint of this is -3.675 + (-0.933) / 2 = -2.3ns! This was my final value that works. when I say I recompiled to get it to work, I mean that after a full recompilation (extra effort - standard fit) in Quartus. This gave different timing so that the numbers came out different and it worked. - Altera_Forum
A better way to calculate how many degree should be shifted is using the oscilloscope or logic analyzer. You can write a simple program, let dma continuously write to or read from SDRAM, from the logic analyzer, you can get how many degrees you should shift.
