Honored Contributor
Honored ContributorFor my design:
clock = 100MHz ~ 10ns. Read Lag = toh(SDRAM)-thmax(FPGA) = 2.5ns-(-5.205ns) = 7.705ns Write Lag = tclk-tco_max(FPGA) - tds(SDRAM) = 10-4.325-2 = 3.675ns Read Lead = tco_min(FPGA) - tdh(SDRAM) = 2.65ns - 1ns = 1.65ns Write Lead = tclk - thz(3)(SDRAM) - tsu_max(FPGA) = 10ns-5.5ns-5.433ns = -0.933ns. Now it says take the lesser of each the lead and lag which would be -3.675 and -0.933. note that I negated the 3.675 which the Altera note deosn't tell you to do, but they did it in their example. the midpoint of this is -3.675 + (-0.933) / 2 = -2.3ns! This was my final value that works. when I say I recompiled to get it to work, I mean that after a full recompilation (extra effort - standard fit) in Quartus. This gave different timing so that the numbers came out different and it worked.
