ContributorThe Cyclone 10GX seems to configure from the programmer but Eclipse fails to connect though the embedded download cable.
I only got this far by checking the 'Ignore mismatched system ID' and 'Ignore mismatched system timestamp' in the Target connection dialog, so I guess I need to fix that somehow.
The programmer JTAG auto-detect looks like this.
Thanks in advance
ContributorHi,
Thank you reaching us.
For elf process failed, usually there a few things you can check. Mainly due to any mistake during the NiosII design, especially connections related to the memory where the ELF file will reside. There also a few things can check before download program to the board such as qsys configuration compilation, verilog connections between qsys generated model and board hardware. For the box "ignore mismatched system ID' and 'ignore mismatched system timestamp", can try uncheck since these checks verify that your software is compiled for the FPGA configuration that is actually loaded on the board.
ContributorCheck a gazillion things isn't really giving me a steer.
The console message is:
09:45:08 **** Incremental Build of configuration Nios II for project AcqTester ****
wsl make all
Info: Building /mnt/c/Users/olivers/Documents/sbsvn/Apogee/CO717-Cyc10/FPGA/eval_c10gx220/AcqNIOS/software/AcqTester_bsp/
make --no-print-directory -C /mnt/c/Users/olivers/Documents/sbsvn/Apogee/CO717-Cyc10/FPGA/eval_c10gx220/AcqNIOS/software/AcqTester_bsp/
[BSP build complete]
[AcqTester build complete]09:45:09 Build Finished (took 1s.157ms)
ContributorHi,
This is the log on make. There should be another log in Eclipse. We are expecting to see the log on eclipse to know either it can pass the processor reset or not.
This is the example of the log if failed the reset processor.
This is the example of the log if success.
You can try use nios2-download command.
$ nios2-download -g -r <>.elf
ContributorBy the way, hope you can share the message in the Console window.
ContributorPlease check the inbox, I already sent the email.
ContributorHi,
Do you have any updates to share about this issue?
ContributorI seem to be in a death spiral, see https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/Is-my-Cyclone-10-GX-development-kit-board-faulty/m-p/1544099#M26381 $1200 spent on this board and I've got nothing out of it.
ContributorHi,
Did the previous suggestion which is to connect the debug_reset_request to processor reset port solved the "downloading ELF process failed" error?
Regarding the debugger cannot connect issue, you also can try to remove the SYSID IP in Platform Designer, then Re-Add it again, then recompile everything and re-try. By the way, is the design from an example design downloaded somewhere?
We sent you an email. Hope you can reply to that as we want to help figuring the reason you cannot reply to the below thread.
ContributorHi,
Do you have any updates to share about this issue?
ContributorMy evaluation board was refusing to configure so I haven't been able to try anything (see https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/Is-my-Cyclone-10-GX-development-kit-board-faulty/m-p/1544844/emcs_t/S2h8ZW1haWx8dG9waWNfc3Vic2NyaXB0aW9ufExQMjhJS05NSjZaWFBYfDE1NDQ4NDR8U1VCU0NSSVBUSU9OU3xoSw#M26394)
It configured this morning so I'll see if I can make any progress with the NIOS.
I did the NIOS platform from scratch because I've never found an example that didn't need a load of changes just to get it to compile with my installed version of Quartus. I've been using the Trenz Cyc1000 NIOS with reasonable success apart from booting from off chip memory, https://community.intel.com/t5/Programmable-Devices/Autostart-NIOS-from-external-SDRAM-problem/m-p/1509971#M91900 which I just gave up on.
ContributorNo change, not sure what else I can say. It's really hard to capture any messages because they get over-written. Waiting 24 hours plus is so frustrating, I start each troubleshooting session having forgotten where I'd got to last time.
ContributorHi,
Glad to know your board now can be configured.
I am working on the Hello World NiosII on Cyclone GX to identify the issue too.
ContributorI am still working on that template, will send to your email once complete.
ContributorHi,
I already test this design and it working on our side. Testing is using the Cyclone 10 (10CX220YF780E5G) and Quartus Prime Pro Edition 23.1. This design was build according to this document https://www.intel.com/content/dam/support/us/en/programmable/support-resources/fpga-wiki/asset02/nios-ii-hello-world-a10.pdf but for the Cyclone 10.
After I built the project, I programed the .sof and able to "Run as > NiosII hardware " in Eclipse and print out hello world in the console. You can try on your board and let us know.
I sent the design to your email and also attached it below this reply.
Disclaimer - This is not official design from Intel, you may use on your own risk.
ContributorThe design attached on this reply.
ContributorHi Oliver,
I will attached the .qar file below this reply. Hope it work on your side.
Thank you.
ContributorDisclaimer : These documents are not official document from Intel.
