Contributor
ContributorCheck a gazillion things isn't really giving me a steer.
The console message is:
09:45:08 **** Incremental Build of configuration Nios II for project AcqTester ****
wsl make all
Info: Building /mnt/c/Users/olivers/Documents/sbsvn/Apogee/CO717-Cyc10/FPGA/eval_c10gx220/AcqNIOS/software/AcqTester_bsp/
make --no-print-directory -C /mnt/c/Users/olivers/Documents/sbsvn/Apogee/CO717-Cyc10/FPGA/eval_c10gx220/AcqNIOS/software/AcqTester_bsp/
[BSP build complete]
[AcqTester build complete]09:45:09 Build Finished (took 1s.157ms)
ContributorHi,
This is the log on make. There should be another log in Eclipse. We are expecting to see the log on eclipse to know either it can pass the processor reset or not.
This is the example of the log if failed the reset processor.
This is the example of the log if success.
You can try use nios2-download command.
$ nios2-download -g -r <>.elf
ContributorA different console message did show but it was cleared before I could capture it.
After trying it a few more times I caught this:
Using cable "USB-BlasterII [USB-1]", device 2, instance 0x00
Pausing target processor: not responding.
Resetting and trying again: FAILED
Leaving target processor paused
Where do I type the nios2-download command?
ContributorHi,
Nios2-download command can be run on Nios2 command shell.
Since you get the processor reset failed error so we suggesting these three possibilities you can look and check.
1. Clock bridge IP frequency is incorrect (between QSYS & actual clock)
2. Reset bridge IP settings (Most common one is the Active Low)
3. Connection between processor debug_reset_request to processor reset
You also can take a look at below link to check on the few solution to fix the issue.
https://www.macnica.co.jp/en/business/semiconductor/articles/intel/133704/
Thank you.
Regards,
Fathulnaim
ContributorAaargh, this is so frustrating! Your screenshot doesn't show what reset is connected to. At the top level I've connected mine to the development board fpga_resetn signal but as per my other forum thread I can't get an explanation of its functionality, see https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/Cyclone-10-GX-dev-kit-which-signal-can-I-use-to-reset-a-NIOS/m-p/1539825#M26240 (BTW I can't post replies to this thread, another source of complete frustration)
In the mean time, here's a screenshot of my Platform Designer.
If there's any way to speed up this dialogue from 24 hour responses please let me know.
