Constraining SDRAM

Hello,

I have a very strange issue on my EP3C55F484, when sometimes Nios II processor works, sometimes - not. One minute I am able to upload the binary, it works fine for a half of a day even if I do a dozen times of re-upload and debug, but suddenly *bam*, it doesn't allow to upload a new binary:

Pausing target processor: not responding.
Reseting and trying again: FAILED
Leaving target processor paused

Sometimes it happens on the beginning of a day, sometimes at the end of the day, but there are no tendencies - completely random issue. I've checked hardware - everything should be fine, all voltages are correct. PLL working fine, no lock losses.

My constraints are not complete or bad, I am not sure where I am doing a mistake, so let's look what I have:

SDRAM chip: Micron MT48LC4M16A2P-75 - datasheet here. (http://www.micron.com/parts/dram/sdram/~/media/documents/products/data%20sheet/dram/47264msdram.ashx)

The Qsys design runs on 62.5MHz, clocked from PLL output 0. The SDRAM chip itself, is clocked @ 62.5MHz -3ns phase shift, PLL output 1.

TimeQuest reports Fmax of 71.5MHz

The first thing to do is to define timing parameters from datasheet:

set SDRAM_PCB_DELAY 0.10
set SDRAM_ACCESS 5.40
set SDRAM_DATA_OUT_HOLD 3.00#  CS#, RAS#, CAS#, WE#, DQM, ADDRESS - will be named as MISC
set SDRAM_MISC_HOLD 0.80
set SDRAM_MISC_SETUP 1.50

Then, I need to define a clock and its output delay:

create_generated_clock -name sdram_sys_clk_pin -source {PLL0|altpll_component|auto_generated|pll1|clk} 
set_output_delay -clock sdram_sys_clk_pin $SDRAM_PCB_DELAY 

Now, constrain I/Os:

set_input_delay -clock sdram_sys_clk_pin -min  }]
set_input_delay -clock sdram_sys_clk_pin -max  }]
set_output_delay -clock sdram_sys_clk_pin -min   sdram_sys_ba
 sdram_sys_dqm
 sdram_sys_ras_n sdram_sys_cas_n sdram_sys_cs_n sdram_sys_we_n}]
set_output_delay -clock sdram_sys_clk_pin -max   sdram_sys_ba
 sdram_sys_dqm
 sdram_sys_ras_n sdram_sys_cas_n sdram_sys_cs_n sdram_sys_we_n}]

Set relationship between clocks:

set_min_delay -0.60 -from {PLL0|altpll_component|auto_generated|pll1|clk} -to {sdram_sys_clk_pin}
set_max_delay 0.52 -from {PLL0|altpll_component|auto_generated|pll1|clk} -to {sdram_sys_clk_pin}

At this point, I should constraint all paths using multicycles, but I am not sure, how multicycles would work in this case. If I add set_max_delay, then the delays are way too long: TQ says I need to add almost 10ns delay, which is strange..?

I am attaching result of: report_timing -setup -npaths 100 -detail full_path -file "TQ_100worstpaths.txt"

You'll see, that I am using 5 SDRAM controllers: 1 for Nios and 4 buffer for data, but the issue is the same for all. It fails timing between I/O pin and first data register (qsys_system|etc|some|controller|stuff|za_data

[*])

P.S. I don't get any hold/removal/recovery violations for that particular clock.

Maybe someone could point me how to solve that setup violation problem and what am I doing wrong? Thank You.