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Honored Contributor
Honored ContributorConstraining SDRAM
Hello, I have a very strange issue on my EP3C55F484, when sometimes Nios II processor works, sometimes - not. One minute I am able to upload the binary, it works fine for a half of a day even if I...
Altera_ForumHonored Contributor
Honored ContributorThe 0.75ns shift was actually already calculated when I started working on that design. I have somewhere the documentation which explains how it has been calculated. If I can find it I'll tell you.
The use of another pll output is correct, That's what I do, too. Do you mind trying to recompile with no i/o constraints and clock phase shift reduced to -0.75ns and check if this way the design works?
