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Honored Contributor
Honored ContributorConstraining SDRAM
Hello, I have a very strange issue on my EP3C55F484, when sometimes Nios II processor works, sometimes - not. One minute I am able to upload the binary, it works fine for a half of a day even if I...
Altera_ForumHonored Contributor
Honored ContributorI'm not a TQ expert, but I guess your problem is the 2.9ns setup relationship between the clocks; I think it will never be met with the specified delays.
Did you try to compile and run the design without all those constraints? Does it work? I have a similar design with same SDRAM device but never had such problems. The only major difference is that my sdram clock shift is only -0.75ns.
