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Honored Contributor
Honored ContributorConstraining SDRAM
Hello, I have a very strange issue on my EP3C55F484, when sometimes Nios II processor works, sometimes - not. One minute I am able to upload the binary, it works fine for a half of a day even if I...
Altera_ForumHonored Contributor
Honored ContributorOk. So, from what can see the problem is as follows
The SDRAM launches data at the rising edge of sdram_sys_clk_pin (@13 ns) and the register captures it at the next rising edge of pll|c0 (@16 ns). So, you only have 3 ns to absorb the delays. Which, as Cris said, will never work. $SDRAM_ACCESS eats up 5.40 ns alone. Plus pin to register delay, clock skew and uncertainty. All in all, you're 7.256 ns short. What you need to to is change the -3ns phase shift value into something else, in order to have more time. -10.256ns does look promising. But 0 is probably the best starting point.
