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Altera_Forum
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14 years ago

Constraining SDRAM

Hello, I have a very strange issue on my EP3C55F484, when sometimes Nios II processor works, sometimes - not. One minute I am able to upload the binary, it works fine for a half of a day even if I...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hm, why did You choose -0.75ns?

According to datasheet page 23, data out hold time (tOH) is 3ns, that's why I am using another PLL output with the same frequency, but different phase shift for the SDRAM chip itself. Afaik it is a common approach to use such clocking method or I am missing something here?

Design without constraints does work exactly the same. Or... I would say doesn't work exactly the same. Completely random. One upload the same binary works, try to upload again - it doesn't...