Constraining SDRAM

Random thoughts

- The datasheet refers a "no-load" data out hold time of 1.8 ns. Try using that value instead of 3.0 ns.

- You're always adding 0.100 ns delay for the PCB. But the PCB delay isn't the always 0.10 and isn't the same for all signals. In particular, the clock may be delayed more or less than the other signals. Also, for signals coming from the SDRAM, you need not only to account for the PCB delay the signals suffer between the SDRAM and the FPGA but also the delay the clock suffers between the FPGA and the SDRAM.

So, I'd use something like this

set_input_delay -clock sdram_sys_clk_pin -min  }]
set_input_delay -clock sdram_sys_clk_pin -max  }]
set_output_delay -clock sdram_sys_clk_pin -min   sdram_sys_ba sdram_sys_dqm sdram_sys_ras_n sdram_sys_cas_n sdram_sys_cs_n sdram_sys_we_n}]
set_output_delay -clock sdram_sys_clk_pin -max   sdram_sys_ba sdram_sys_dqm sdram_sys_ras_n sdram_sys_cas_n sdram_sys_cs_n sdram_sys_we_n}]

A final matter I didn't get: with these constraints alone, do you get timing violations in TQ or not?