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Honored Contributor
Honored ContributorConstraining SDRAM
Hello, I have a very strange issue on my EP3C55F484, when sometimes Nios II processor works, sometimes - not. One minute I am able to upload the binary, it works fine for a half of a day even if I...
Altera_ForumHonored Contributor
Honored ContributorHm, that's strange, but looks interesting. Anyway, if I use phase shifted clock method, I know that I need to use multicycles. If I understand correctly, if I set multicycle 2 for setup, then the data should be sampled on the second rising edge of the pll|c0, which should give me additional 16ns?
Sorry, I am not exactly sure what multicycle does. Actually, it is strange, that in my case, I need to use such a long delay, when Cris told, that he use way smaller phase difference. EDIT: I've tried to set phase difference to -10.2ns. This obviously helps TimeQuest to show me, that there are no setup violations made, but if I try to upload Nios design (at least it allows to try to upload!), it says that verify has failed between some addresses... Now trying other options.
