Honored ContributorHi All,
I'm working on a research project involving NiosII processor. We need to be able to control cache bypass signal. Can any of you guide me how to do that? I need to instantiate the NiosII without cache and instantiate the cache module as another IP connected to Data bus or Instruction bus, depending on my needs.
Honored ContributorYou can't separate the caches from the processor itself.
For systems without the mmu, the cache can be bypassed by either using the ldio/stio instructions or setting the most significant address bit. The altera documentation for the cpu explains all of this.Honored ContributorThank you for your reply.
Can you tell me if I can bypass the Instructions cache? Is there a special Instruction to bypass or turns off the cache?Honored ContributorInstrcutions can only be read from the I-cache or from tightly coupled instruction memory. Even if uncached code accesses were supported they would be very very slow.
If you are executing from internal memory you probably ought to make it 'tightly coupled' instruction memory - saving the logic and memory blocks needed for the instruction cache.Honored ContributorI'm doing a research project. And I need to bypass the I-cache at certain points of execution.
Honored ContributorHonored ContributorIt's not possible with the current core and I don't think it is planned for the future. The only way I can think of would be to invalidate the corresponding entries in the instruction cache to force it to re-read the instruction from memory.
Honored ContributorThese don't address what you are looking for but they are worth mentioning anyway just in case...
1) If you don't want an instruction cache you can instantiate the 'e' core. Note: like others have said the performance will drop as a result. 2) If you place code that you don't want cached in a tightly coupled instruction memory then the instruction cache will not be accessed when the program counter hits that memory region. Note: tightly coupled memories have single cycle access times so if you were looking for higher latency this is not something feasible. If you post why you need to perform instruction fetches that bypass the instruction cache maybe you'll get an answer closer to what you are looking for. Maybe the Cortex-M1 will accomplish what you are looking for: http://www.altera.com/devices/processor/arm/cortex-m1/m-arm-cortex-m1.htmlHonored ContributorI am wondering why on chip memory is cached by nios2?
Is on chip memory as fast as nios2? Is there a way to avoid caching on chip memory content?Honored ContributorThe CPU caches everything that is connected to its data and instruction masters by default. You can either use uncached memory pointers in the software code to avoid the cache, or connect the on chip memories to tightly coupled masters, that will avoid the cache.
Honored Contributor
