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Altera_Forum's avatar
Altera_Forum
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14 years ago

Cache Implmentation

Hi All, I'm working on a research project involving NiosII processor. We need to be able to control cache bypass signal. Can any of you guide me how to do that? I need to instantiate the Nios...
Altera_Forum's avatar
Altera_Forum
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14 years ago

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I am wondering why on chip memory is cached by nios2?

Is on chip memory as fast as nios2?

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As Daixiwen said, Nios caches everything connected to its data and instruction masters. This is consistent, since in general you can have multi-master buses and your cpu would stall when another master is accessing the bus. Using cache also for onchip memory reduces the frequency of such a situation.

Tightly coupled memory takes advantage of a dedicated port, so it doesn't need to be cached.