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Altera_Forum's avatar
Altera_Forum
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14 years ago

Cache Implmentation

Hi All, I'm working on a research project involving NiosII processor. We need to be able to control cache bypass signal. Can any of you guide me how to do that? I need to instantiate the Nios...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

It's not possible with the current core and I don't think it is planned for the future. The only way I can think of would be to invalidate the corresponding entries in the instruction cache to force it to re-read the instruction from memory.