Honored ContributorHi All,
I'm working on a research project involving NiosII processor. We need to be able to control cache bypass signal. Can any of you guide me how to do that? I need to instantiate the NiosII without cache and instantiate the cache module as another IP connected to Data bus or Instruction bus, depending on my needs.
Honored ContributorUncached memory accesses to Avalon slaves are also slower than accesses to cache (and tightly coupled memory - which is a bit like pre-filled cache!)
Since internal memory is dual ported, you can give the cpu 'tightly coupled' access and allow other masters to access via the Avalon 'bus'. Give the cpu 'data' access to its own code. This works best if you can separate out the code (without any data) into a separate memory area (the Altera provided linker script doesn't do this, and their gcc4 build directly embeds data (jump tables) in the code segment!). You'll still need an instruction cache if you want to use any of the Altera boot code or JTAG debug - since they don't export both ports of the relevant memory areas so the contained code can't be 'tightly coupled'.Honored ContributorIs there any CPU that allows bypassing its I-cache by turn it on and off as required?
Honored ContributorThe only time any modern cpu is usually run with the instruction cache disabled is immediately after reset. There is usually no reason to turn it off!
Special consideration has to be made for self modifying code (etc). You can certainly run a 68020 with its I-cache disabled! and probably some of the ARM cores. Any x86 chip - especially in 'real' mode. But since disabling the I-cache kills performance, the first thing anyone does is enable it!Honored Contributor
