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Altera_Forum
Honored Contributor
Honored ContributorCache Implmentation
Hi All, I'm working on a research project involving NiosII processor. We need to be able to control cache bypass signal. Can any of you guide me how to do that? I need to instantiate the Nios...
Altera_ForumHonored Contributor
Honored ContributorInstrcutions can only be read from the I-cache or from tightly coupled instruction memory. Even if uncached code accesses were supported they would be very very slow.
If you are executing from internal memory you probably ought to make it 'tightly coupled' instruction memory - saving the logic and memory blocks needed for the instruction cache.
