Forum Discussion
New ContributorWhy is there no output in PLL simulation?
I instantiated a PLL in my design, refclk is 50MHz, 3 output clocks are 500MHz, 50MHz, 25MHz respectivily, and I enalbe dynamic phase shift option. But only the output 500MHz is valid, the other two output is x in the simulation. I just used the auto-generated pll simulation test bench. My quartus software is 16.1, and the device is cyclone V 5CEFA4.
7 Replies
Vicky1Regular Contributor
Hi,
Could you please refer the below reference design for Dynamic phase shift with Intel PLL IP core
Please let me know, how it works to you.
Regards,
Vicky
JLIU45Hi, Vicky: thanks for your reply, I checked the design and understand that. However, my confusing is that the simulation cannot work, and I used the auto-generated simulation testbench. below is my simulation waveform, FYI, only outclk_0(500MHz) is valid, the other two is x. BR Liu Jianjun
AndyNOccasional Contributor
What timeunit are you simulating with? PLL simulations can be really tricky about wanting a very fine grained simulation so I'd recommend trying with timeunit 1fs/1fs; and see if you get any different results.
- JLIU45Hi, Andy: thanks of ryour reply! I tried 1fs timeunit, still the same result. It's puzzling that only 500MHz output can be seen, and the other two output clocks are x. I also simulated the PLL without dynamic phase shift function, it works well. Did you run the auto-generated simulation testbench? BR Liu Jianjun
- Vicky1
Hi,
Please follow the steps as mentioned in below application notes,
https://www.intel.com/content/www/us/en/programmable/documentation/mcn1424769382940.html#mcn1424940703121
please let me know, how it works for you.
Regards,
Vicky
- JLIU45Hi, Vicky: I think I've solved the problem, just because this PLL needs a POR, however, this operation is not necessary for other PLLs, anyway I can run the simulation, thank you very much. BR Liu Jianjun
- Vicky1
Hi Liu Jianjun,
Glad you resolved it.
Thanks,
Vicky
