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JLIU45's avatar
JLIU45
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6 years ago

Why is there no output in PLL simulation?

I instantiated a PLL in my design, refclk is 50MHz, 3 output clocks are 500MHz, 50MHz, 25MHz respectivily, and I enalbe dynamic phase shift option. But only the output 500MHz is valid, the other two ...
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    JLIU45
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    6 years ago
    Hi, Vicky: thanks for your reply, I checked the design and understand that. However, my confusing is that the simulation cannot work, and I used the auto-generated simulation testbench. below is my simulation waveform, FYI, only outclk_0(500MHz) is valid, the other two is x. BR Liu Jianjun