Forum Discussion
JLIU45
New Contributor
New ContributorWhy is there no output in PLL simulation?
I instantiated a PLL in my design, refclk is 50MHz, 3 output clocks are 500MHz, 50MHz, 25MHz respectivily, and I enalbe dynamic phase shift option. But only the output 500MHz is valid, the other two ...
Vicky1
Regular Contributor
Regular ContributorHi,
Could you please refer the below reference design for Dynamic phase shift with Intel PLL IP core
Please let me know, how it works to you.
Regards,
Vicky
JLIU45Hi, Vicky: thanks for your reply, I checked the design and understand that. However, my confusing is that the simulation cannot work, and I used the auto-generated simulation testbench. below is my simulation waveform, FYI, only outclk_0(500MHz) is valid, the other two is x. BR Liu Jianjun
