Forum Discussion
JLIU45
New Contributor
New ContributorWhy is there no output in PLL simulation?
I instantiated a PLL in my design, refclk is 50MHz, 3 output clocks are 500MHz, 50MHz, 25MHz respectivily, and I enalbe dynamic phase shift option. But only the output 500MHz is valid, the other two ...
AndyN
Occasional Contributor
Occasional ContributorWhat timeunit are you simulating with? PLL simulations can be really tricky about wanting a very fine grained simulation so I'd recommend trying with timeunit 1fs/1fs; and see if you get any different results.
JLIU45Hi, Andy: thanks of ryour reply! I tried 1fs timeunit, still the same result. It's puzzling that only 500MHz output can be seen, and the other two output clocks are x. I also simulated the PLL without dynamic phase shift function, it works well. Did you run the auto-generated simulation testbench? BR Liu Jianjun
