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JLIU45's avatar
JLIU45
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6 years ago

Why is there no output in PLL simulation?

I instantiated a PLL in my design, refclk is 50MHz, 3 output clocks are 500MHz, 50MHz, 25MHz respectivily, and I enalbe dynamic phase shift option. But only the output 500MHz is valid, the other two ...
AndyN's avatar
AndyN
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

What timeunit are you simulating with? PLL simulations can be really tricky about wanting a very fine grained simulation so I'd recommend trying with timeunit 1fs/1fs; and see if you get any different results.

  • JLIU45's avatar
    JLIU45
    Icon for New Contributor rankNew Contributor
    6 years ago
    Hi, Andy: thanks of ryour reply! I tried 1fs timeunit, still the same result. It's puzzling that only 500MHz output can be seen, and the other two output clocks are x. I also simulated the PLL without dynamic phase shift function, it works well. Did you run the auto-generated simulation testbench? BR Liu Jianjun