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JLIU45's avatar
JLIU45
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6 years ago

Why is there no output in PLL simulation?

I instantiated a PLL in my design, refclk is 50MHz, 3 output clocks are 500MHz, 50MHz, 25MHz respectivily, and I enalbe dynamic phase shift option. But only the output 500MHz is valid, the other two ...
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    JLIU45
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    6 years ago
    Hi, Vicky: I think I've solved the problem, just because this PLL needs a POR, however, this operation is not necessary for other PLLs, anyway I can run the simulation, thank you very much. BR Liu Jianjun