Forum Discussion
JLIU45
New Contributor
New ContributorWhy is there no output in PLL simulation?
I instantiated a PLL in my design, refclk is 50MHz, 3 output clocks are 500MHz, 50MHz, 25MHz respectivily, and I enalbe dynamic phase shift option. But only the output 500MHz is valid, the other two ...
Vicky1
Regular Contributor
Regular ContributorHi,
Please follow the steps as mentioned in below application notes,
https://www.intel.com/content/www/us/en/programmable/documentation/mcn1424769382940.html#mcn1424940703121
please let me know, how it works for you.
Regards,
Vicky
JLIU45Hi, Vicky: I think I've solved the problem, just because this PLL needs a POR, however, this operation is not necessary for other PLLs, anyway I can run the simulation, thank you very much. BR Liu Jianjun
