Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Why I can't simulate Triple-Speed Ethernet MegaCore?

Hello community,

I hope for your help. I have 2 problems with simulation of Triple Speed Ethernet Megacore (TSE):

Programming in VHDL with

Quartus II 64-Bit Version 15.0.0 Build 145 04/22/2015 SJ Web Edition

Simulation with

ModelSim ALTERA STARTER EDITION 10.3d

TSE is generated with MegaWizard, Example Design is also generated

problem 1: tse doesn't seem to be bounded correctly in test bench

- i want to simulate read and write over SPI from/to the registers of TSE (later of course I will simulate some other functions of TSE)

- NativeLink and a test bench with the file TSE_MegaCore.vhd (my variation from the TSE) from the directory TSE_MegaCore is used

- Tools -> Run Simulation Tool -> Gate Level Simulation...

- Signal reg_busy stays on initial value, but TSE registers are addressed, data is writen to reg_data_in and signal reg_wr (or reg_rd) is set to '1'

- register of TSE are not showed under Memory List in Model Sim

- Warning ModelSim/Transcript:

# ** Warning: (vsim-3473) Component instance "i_tse_mac : altera_eth_tse_mac" is not bound.

# Time: 0 ps Iteration: 0 Instance: /test_spi/ZuTestendesModul/TRIPLE_SPEED_ETHERNET_MEGACORE File: C:/Users/matthiask/Masterarbeit/FPGA_Ethernet_Funktion/FPGA_Ethernet_Funktion/TSE_MegaCore_sim/TSE_MegaCore.vhd

# ** Warning: (vsim-8684) No drivers exist on out port /test_spi/ZuTestendesModul/TRIPLE_SPEED_ETHERNET_MEGACORE/reg_data_out, and its initial value is not used.

#

# Therefore, simulation behavior may occur that is not in compliance with

#

# the VHDL standard as the initial values come from the base signal /test_spi/ZuTestendesModul/sv32TSERegisterDatenAnSPI.

#

# ** Warning: (vsim-8684) No drivers exist on out port /test_spi/ZuTestendesModul/TRIPLE_SPEED_ETHERNET_MEGACORE/reg_busy, and its initial value is not used.

#

# Therefore, simulation behavior may occur that is not in compliance with

#

# the VHDL standard as the initial values come from the base signal /test_spi/ZuTestendesModul/sTSERegisterbeschaeftigt.

#

# ** Warning: (vsim-8684) No drivers exist on out port /test_spi/ZuTestendesModul/TRIPLE_SPEED_ETHERNET_MEGACORE/eth_mode, and its initial value is not used.

and so on.

What's the Problem?

Which files I have further to add to the testbench?

Or are wrong settings the problem?

problem 2: simulating test bench after ,,triple-speed ethernet megacore function user guide'', chapter 10, fails

- launching Quartus II, open project generate_sim.qpf from directory TSE_MegaCore_testbench

- on the Tools menu, I select Tcl Scripts and select the generate_sim_vhld.tcl file and I clicked run

- message ,,Tcl Script File C:/Users.../generate_sim_vhdl.tcl executed''

- in directory Project/testbench_vhdl/TSE_MegaCore run_TSE_MegaCore_tb.tcl selected and executed

- message ,,Tcl Script File C:/Users.../run_TSE_MegaCore_tb.tcl executed''

and now?

- I want to start ModelSim: Tools -> Run Simulation Tool -> Gate Level Simulation...

- message ,,Can't find file C:/Users/.../TSE_MegaCore_testbench/generate_sim.sft. Run the EDA Netlist Writer''

- I startet the EDA Netlist Writer

- after a few seconds error massages:

Error (12007): Top-level design entity "generate_sim" is undefined

Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 1 error, 1 warning

Error: Peak virtual memory: 670 megabytes

Error: Processing ended: Fri Jan 29 10:13:05 2016

Error: Elapsed time: 00:00:12

Error: Total CPU time (on all processors): 00:00:26

Error (293001): Quartus II Flow was unsuccessful. 3 errors, 1 warning

- why there isn't in the project a file named generate_sim (generate_sim.vhd?) ?

are my own VHDL project and the testbench provided with the Triple-Speed Ethernet MegaCore independent from each other?

so: how I can simulate the Triple-Speed Ethernet MegaCore?

Greetings, Matthew

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Hi community,

    maybe the TSE is a special component, what is not often used, but what about PLLs?

    I haven't solved the problem with the TSE, but I have to go further, so I implemented a very simple PLL (Altera PLL from the IP catalog in Quartus II, not from Qsys).

    Look, I got this Warning, when I wanted to start ModelSim

    # ** Warning: (vsim-3473) Component instance "i_tse_mac : altera_eth_tse_mac" is not bound.

    # Time: 0 ps Iteration: 0 Instance: /test_spi/ZuTestendesModul/TRIPLE_SPEED_ETHERNET_MEGACORE File: C:/Users/.../FPGA_Ethernet_Funktion/FPGA_Ethernet_Funktion/TSE_MegaCore_sim/TSE_MegaCore.vhd

    # ** Warning: (vsim-3473) Component instance "meine_pll_inst : Meine_PLL_0002" is not bound.

    # Time: 0 ps Iteration: 0 Instance: /test_spi/ZuTestendesModul/TAKT_GENERATOR File: C:/Users/.../FPGA_Ethernet_Funktion/FPGA_Ethernet_Funktion/Meine_PLL.vhd

    # ** Warning: (vsim-8684) No drivers exist on out port /test_spi/ZuTestendesModul/TRIPLE_SPEED_ETHERNET_MEGACORE/reg_data_out, and its initial value is not used.

    #

    # Therefore, simulation behavior may occur that is not in compliance with

    #

    # the VHDL standard as the initial values come from the base signal /test_spi/ZuTestendesModul/sv32TSERegisterDatenAnSPI.

    #

    # ** Warning: (vsim-8684) No drivers exist on out port /test_spi/ZuTestendesModul/TRIPLE_SPEED_ETHERNET_MEGACORE/reg_busy, and its initial value is not used.

    #

    # Therefore, simulation behavior may occur that is not in compliance with

    #

    # the VHDL standard as the initial values come from the base signal /test_spi/ZuTestendesModul/sTSERegisterbeschaeftigt.

    #

    # ** Warning: (vsim-8684) No drivers exist on out port /test_spi/ZuTestendesModul/TRIPLE_SPEED_ETHERNET_MEGACORE/eth_mode, and its initial value is not used.

    #

    # Therefore, simulation behavior may occur that is not in compliance with

    #

    # the VHDL standard as the initial values come from the base signal /test_spi/ZuTestendesModul/sTSEEthMode.

    etc.

    For TSE and the PLL the same warning. So I think, this couldn't be a TSE specific problem.

    I can simulate my registers, my spi, my RAM. but I can't get any signals from the TSE or the PLL (I still just want to write to the TSE registers; I haven't connected every signal in the port map of TSE, just the ones I think I need to have access to the registers).

    I still use NativeLink and have added TSE_MegaCore_sim/TSE_MegaCore.vhd and Meine_PLL.vhd to my test bench.

    So, what have I forgotten? Where's the failure? What I'm doing wrong?

    I would be lucky, if you can help me to simulate my whole system.

    Greetings, Matthew
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Gate level simulation isn't supported on some devices, and this may be part of your problem.

    Do you have the same difficulty with RTL simulation?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Hi ted,

    from Quartus II I started ,,RTL simulation''. ModelSim generates a very long compilation report, unfortunately with an error:

    ...

    # vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver -L rtl_work -L work -L Meine_PLL -L i_tse_mac -voptargs="+acc" Test_SPI

    # vsim -gui "+altera" -l msim_transcript -do "Ethernet_Modul_run_msim_rtl_vhdl.do"

    # Start time: 11:43:12 on Feb 17,2016

    # Loading std.standard

    # Loading std.textio(body)

    # Loading ieee.std_logic_1164(body)

    # Loading ieee.std_logic_arith(body)

    # Loading ieee.std_logic_unsigned(body)

    # Loading work.test_spi(test_spi_verhalten)

    # Loading work.fpga_register_allgemein(body)

    # Loading work.ethernet_modul(ethernet_funktion)

    # Loading work.spi_schnittstelle_synchron(behavioral)

    # Loading ieee.numeric_std(body)

    # Loading work.verdrahtete_logik(body)

    # Loading work.fpga_register_funktion(verhalten_register_funktion)

    # Loading altera_mf.altera_mf_components

    # Loading work.onchipmemoryram(syn)

    # Loading altera_mf.altera_common_conversion(body)

    # Loading altera_mf.altera_device_families(body)

    # Loading altera_mf.altsyncram(translated)

    # Loading work.tse_megacore(rtl)

    # ** Fatal: Error occurred in protected context.

    # Time: 0 ps Iteration: 0 Protected: /test_spi/ZuTestendesModul/TRIPLE_SPEED_ETHERNET_MEGACORE/i_tse_mac/genblk8/U_RGMII/the_rgmii_in4 File: nofile

    # FATAL ERROR while loading design

    # Error loading design

    # Error: Error loading design

    # Pausing macro execution

    # MACRO ./Ethernet_Modul_run_msim_rtl_vhdl.do PAUSED at line 154

    Okay, this looks like you're right. (But I don't get any messages like that when I start ,,Gate Level Simulation''.)

    But what about the PLL? This component is used by many engeneers, students and so on. I can't really imagine, ModelSim isn't able to simulate these cores.

    Back to my old problem:

    I can't correct read (and maybe write) to the TSE registers. Here an example: I just want to read the TSE registers. I do a hardware reset and then in register 0x11 of the TSE there have to be the data 0xFFFF. But I read 0x482 or nonsense like that.

    I use the same code to write and read to On-Chip Memory RAM and it works.

    Kind regards, Matthew
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Hi,

    I have solved Problem 2: simulating test bench after ,,Triple-Speed Ethernet MegaCore Function User Guide'', Chapter 10:

    - launching Quartus II, open project generate_sim.qpf from directory TSE_MegaCore_testbench

    - on the Tools menu, I select Tcl Scripts and select the generate_sim_vhld.tcl file and I clicked run

    - message ,,Tcl Script File C:/Users.../generate_sim_vhdl.tcl executed''

    and then I have to start ModelSim from the desktop (not from Quartus - this causes an error), navigating in the Transcript window to the folder, where is

    run_TSE_MegaCore_tb.tcl stored (C:\Users\...\FPGA_Ethernet_Funktion\FPGA_Ethernet_Funktion\TSE_MegaCore_testbench\testbench_vhdl\TSE_MegaCore,

    type ,,cd'' for changing directory, type ,,dir'' to see the directories and files of the current folder)

    and type ,,do run_TSE_MegaCore_tb.tcl'' in the transcript window.

    Compilation of needed files is done automatic and simulation works fine!

    Greetings, Matthew