Why I can't simulate Triple-Speed Ethernet MegaCore?

Hi community,

maybe the TSE is a special component, what is not often used, but what about PLLs?

I haven't solved the problem with the TSE, but I have to go further, so I implemented a very simple PLL (Altera PLL from the IP catalog in Quartus II, not from Qsys).

Look, I got this Warning, when I wanted to start ModelSim

# ** Warning: (vsim-3473) Component instance "i_tse_mac : altera_eth_tse_mac" is not bound.

# Time: 0 ps Iteration: 0 Instance: /test_spi/ZuTestendesModul/TRIPLE_SPEED_ETHERNET_MEGACORE File: C:/Users/.../FPGA_Ethernet_Funktion/FPGA_Ethernet_Funktion/TSE_MegaCore_sim/TSE_MegaCore.vhd

# ** Warning: (vsim-3473) Component instance "meine_pll_inst : Meine_PLL_0002" is not bound.

# Time: 0 ps Iteration: 0 Instance: /test_spi/ZuTestendesModul/TAKT_GENERATOR File: C:/Users/.../FPGA_Ethernet_Funktion/FPGA_Ethernet_Funktion/Meine_PLL.vhd

# ** Warning: (vsim-8684) No drivers exist on out port /test_spi/ZuTestendesModul/TRIPLE_SPEED_ETHERNET_MEGACORE/reg_data_out, and its initial value is not used.

#

# Therefore, simulation behavior may occur that is not in compliance with

#

# the VHDL standard as the initial values come from the base signal /test_spi/ZuTestendesModul/sv32TSERegisterDatenAnSPI.

#

# ** Warning: (vsim-8684) No drivers exist on out port /test_spi/ZuTestendesModul/TRIPLE_SPEED_ETHERNET_MEGACORE/reg_busy, and its initial value is not used.

#

# Therefore, simulation behavior may occur that is not in compliance with

#

# the VHDL standard as the initial values come from the base signal /test_spi/ZuTestendesModul/sTSERegisterbeschaeftigt.

#

# ** Warning: (vsim-8684) No drivers exist on out port /test_spi/ZuTestendesModul/TRIPLE_SPEED_ETHERNET_MEGACORE/eth_mode, and its initial value is not used.

#

# Therefore, simulation behavior may occur that is not in compliance with

#

# the VHDL standard as the initial values come from the base signal /test_spi/ZuTestendesModul/sTSEEthMode.

etc.

For TSE and the PLL the same warning. So I think, this couldn't be a TSE specific problem.

I can simulate my registers, my spi, my RAM. but I can't get any signals from the TSE or the PLL (I still just want to write to the TSE registers; I haven't connected every signal in the port map of TSE, just the ones I think I need to have access to the registers).

I still use NativeLink and have added TSE_MegaCore_sim/TSE_MegaCore.vhd and Meine_PLL.vhd to my test bench.

So, what have I forgotten? Where's the failure? What I'm doing wrong?

I would be lucky, if you can help me to simulate my whole system.

Greetings, Matthew