Altera_ForumHonored Contributor10 years agoWhy I can't simulate Triple-Speed Ethernet MegaCore? Hello community, I hope for your help. I have 2 problems with simulation of Triple Speed Ethernet Megacore (TSE): Programming in VHDL with Quartus II 64-Bit Version 15.0.0 Build 145 04/2...Show More
Recent DiscussionsAgilex3/5 GTS Hard Ethernet IP 10G example design pin loc and io std wantedAgilex 7 I Series Development Kit: External hardware access error when programmingInquiry: Reference Clock Jitter Limits for 1G Operation on Agilex 5F-tile 10GBASE-R firecode FEC IP (Agilex 7)F-Tile Ethernet Hard IP Design Example - Testbench