Video Clocked output and VGA

Sukiminna I'm experiencing the same problems that you are. I am working with a DE2 board and I have the following system:

Test_Pattern -> Framebuffer -> CVO

I have configured my peripherals the same way you have done it and the results are the same (flickering and incorrect bars). Have you managed to solve your problems?

Does anybody know if it is a Quartus problem in sp1?

Thanks a lot for your help

Pablo

wich are your :

frame buffer settings

sdram controller settings

sdram clock settings

vga refresh(or pixel clock)

the other parameters that are parametrizable in video pipeline..

Hi Phate,

Thanks a lot for the reply. Here are the parameters:

Test_pattern: 640x480 8bits Parallel Progressive

Framebuffer: 640x480 8bits 3 planes in Parallel

Frame dropping and Frame repetition

1 non-image data packet per frame (length=10)

Avalon memory-mapped interfaces: 64-32-16-32-16

SDRAM Controller: Data width 16

Chip select 1, Banks 4

Row 12, Column 8

Clocked video output should be Ok, because when I try Test_Pattern -> CVO it works.

SDRAM clock is 50MHz and VGA Clock is 25MHz

My system clock is 50MHZ

Are there any other interesting parameter in this case?

Thank you again for your help.

Kind regards

I think you don't have enouch bandwidth in your sdram.

Try to use 5 bit per pixel per color plane and a sdram clock of 100MHz, it sould work.

greetings

Phate

You are right. I used 5 bits per pixel and it worked! Thanks a lot for your help.

I have another question and I wish you could give me any clue. I am trying to use a camera with a CameraLink interface as video source.

My aim is to conect the camera to the CVI and buffer the video into the SDRAM.

However I don't know if I will be able to do this. This CameraLink interface has the following timing signals:

Frame Valid (FVAL): is defined high for valid lines

Line Valid (LVAL): is defined high for valid pixels

Data Valid (DVAL): when data is valid

Do you know if this signals could be directly connected to v_sync, h_sync and datavalid in CVI? I am not sure about the meaning of the CVI sync signals . I did some tests and CVI does not recognize the resolution of the incoming video...

Thank you very much for your help :)

well, honestly, I don't know what is a Cameralink.

As soon as you are using a DE2 and CVI, you have to connect the outputs from your ADV to your CVI (a quick search into the forum should give you lots of hints or answers about that!).

I think (but still, i did not try) that CVI works fine:you have to set up the ADV to recognise your video format. You can perform that operation using opencore's I2C or even "altera audio and video config" ip.

best regards

Phate.

Hello,everyone.

This is my first post,and I can't use English very well.

I'm sorry if there is mistake.

I'm looking for VIP data,bat I can't find it.

If it is ok could you please forward me the data.

could you please upload your project sukiminna or phate

thanks

I'v designed the same thing as you guys, but the problem is that my proj is stuck at compilation ??? 1% left it of 24hrs but it didnt progress further, any ideas what might be wrong,

quartus II 9.1sp2 on windows 7 ( running as admin and windows xp sp3 compatability)

I am not getting errors while building in sopc just a

# 2011.05.20 13:48:11 (*) Plaintext license not found.

# 2011.05.20 13:48:11 (*) No license required to generate encrypted Nios II/e.

but get this at the end

# 2011.05.20 13:49:30 (*) SUCCESS: SYSTEM GENERATION COMPLETED.

Info: System generation was successful.

please help me out

Those aren't error messages. Since Quartus 10 (9?) the Nios II/e core doesn't require a license. The SOPC system was generated successfully.

Where is Quartus stuck? What's the last message in the log?