New ContributorStratix 10 H-Tile Avalon Streaming PCIe IP Core - Root Port Configuration Space access
Hello,
I'm using the L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express configured as Root-Port on a Stratix 10 MX FPGA.
My question is, how do I access the Root-Ports configuration space from my application logic?
I couldn't find any information how to do so in User Guide of the Stratix-10 Avalon Streaming PCIe IP Core.
The User-Guide for the Arria10 and Cyclone 10 GX Avalon Streaming IP-Core, on the other hand, has a chapter (chapter 10.2) that tells to access Root-Ports configuration space by issuing Configuration Requests of Type-0 on the AVST TX Interface.
Quote:
- In Root Port mode, the Application Layer can issue Type 0 or Type 1 Configuration TLPs on the Avalon-ST TX bus.
- The Type 0 Configuration TLPs are only routed to the Configuration Space of the Hard IP and are not sent downstream on the PCI Express link.
As I couldn't find any such information in the User Guide of the Stratix-10 IP Core I tried to do the same with my Stratix-10 design. However, configuration request of Type-0 are forwarded downstream to the Endpoint on the other side of the PCIe-Link.
Any help is appreciated!
Kind regards.
