Forum Discussion

tm1701's avatar
tm1701
Icon for New Contributor rankNew Contributor
2 years ago

Stratix 10 H-Tile Avalon Streaming PCIe IP Core - Root Port Configuration Space access

Hello, I'm using the L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express configured as Root-Port on a Stratix 10 MX FPGA. My question is, how ...
Pcie
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,


The best thing I can do is file an internal ticket to the document team to request emphasis on the importance of having TLP Routing information in Stratix 10 document.

Hope they will add that in the coming release document.


Meanwhile, is there anything else I can help/clarify?


Regards,

Wincent_Intel