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tm1701's avatar
tm1701
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2 years ago

Stratix 10 H-Tile Avalon Streaming PCIe IP Core - Root Port Configuration Space access

Hello, I'm using the L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express configured as Root-Port on a Stratix 10 MX FPGA. My question is, how ...
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  • tm1701's avatar
    tm1701
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    2 years ago

    Hello,

    @Wincent_Altera wrote:

    Hi,

    If I check the KDB below

    https://www.intel.com/content/www/us/en/support/programmable/articles/000080857.html

    Type 0 Root Port Mode Configuration Requests capability for Stratix 10 is not supported.

    Let me know in case I missunderstand your question. Hope that answered your question.

    Regards,

    Wincent_Intel


    thank you for the swift response, this answers my question.

    However I have a follow up question:

    The aforementioned Arria10 and Cyclone 10 GX Avalon Streaming IP-Core User Guide further mentions rules regarding the routing of TLPs in Chapter 10.2.

    Specifically it notes:

    "The Transaction Layer sends all memory and I/O requests, as well as completions generated by the Application Layer and passed to the transmit interface, to the PCI Express link."

    Does this statement hold true for the Stratix-10 HIP core aswell?

    If I get this statement right, it effectively means the base and limit registers in the Root-Ports Type-1 configuration space header are ignored.

    Thank you and kind regards!