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tm1701's avatar
tm1701
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2 years ago

Stratix 10 H-Tile Avalon Streaming PCIe IP Core - Root Port Configuration Space access

Hello, I'm using the L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express configured as Root-Port on a Stratix 10 MX FPGA. My question is, how ...
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  • tm1701's avatar
    tm1701
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    2 years ago

    Thank you once again for your response!

    The reason I refer to the Arria10, Cyclone 10 User Guide, is because I cannot find any Information regarding TLP-Routing in the Stratix 10 User Guide.

    However, I think that information is also necessary on the Stratix 10 to properly use the PCIe IP-Core. My experience from Simulation suggests, that the Stratix 10 Root-Port IP-Core does indeed forward all Memory-Request to the PCIe-Link, ignoring Memory Base and Limit Registers in the Root-Ports Configuration Space Header.
    It would be reassuring to know, whether that's the intended way to use the IP-Core.