Hi, I have another problem about scaler, it's right that adding a control port to scaler makes the input resolution changable, but some resolution doesn't work. My data path is listed below. Clocked Video Input(CVI) -> Scaler(SCL) -> Frame Buffer(FB) -> Mixer(with Test Pattern) -> Clocked Video Output(CVO) The settings of SCL please see the attachments During run-time, I changed the output size of scaler to 1024x768, and I started to change the input resolution, all the resolutions above and include 800x600 worked pretty fine. But when I set the resolution below 800x600, like 720x480 or 640x480, it flickered badly. Any reply is appreciated!

This is just a guess. How deep is the FIFO on your CVI block? Because you are upscaling you are going to put backpressure from the scaler to the CVI. It may be that this backpressure is causing an overflow in your CVI. Jake

--- Quote Start --- This is just a guess. How deep is the FIFO on your CVI block? Because you are upscaling you are going to put backpressure from the scaler to the CVI. It may be that this backpressure is causing an overflow in your CVI. Jake --- Quote End --- Hi, Jake, thanks for your reply! Yes, your guess is right, when I change the input resolution 640x480@60 to 640x480@30, which reduced the backpressure on CVI, it worked well, but it seems hard to set a appropriate size for the FIFO of CVI. In the user guide, you know, it mentioned that the latency of scaler is N(Tap)-1 lines, in my understanding, does it mean that a overflow of CVI won't happen as long as the FIFO depth of CVI is equal to or more than (N-1)lines. Again thanks for reply!

It's a balance between clock frequency and fifo size. Basically when you upscale, the scaler has to use the same input line of data more than once to produce the output. This will hold off the input by at least a line. If during that time your CVI FIFO overflows, then you're in trouble. Now if you're running the VIP blocks fast enough, the scaler can chew through that second line of output and start pulling data again from the input before the FIFO gets a chance to overflow. It's actually a fairly complex calculation to find the exact frequency. Taking into account the vertical and horizontal blanking interval and the input sample frequency at exactly what point will your FIFO overflow. However, if you always run your VIP blocks at at least 2X the input clock frequency of any standard that will be upscaled, you'll probably avoid the issue. Jake

Hi ; I'm working with scaler to upscale from 800x600 to 1080P, but I don't have anything in the screen or in the est case I get a flicker. I'm using Altera Cyclone III development board. and here the chain that I'm using in sopc builder. CVI->scaler->video frame buffer -> CVO Does anayone have an resolution for this problem ? thank you. Rabia

Hi, lots of things could be wrong in this system. You need to get this system working first: TPG->CVO (where TPG is the test pattern generator) Then you can try: TPG->frame buffer->CVO Then: TPG->scaler->frame buffer->CVO And finally: CVI->scaler->frame buffer->CVO

scaler problem | Altera Community

32 Replies

Altera_Forum
Honored Contributor
15 years ago
--- Quote Start ---
Hi,
Is there any overflow or underflow occured when you insert a scaler?
If a overflow occured, may be you could increase the buffer of the cvi.
Sean
--- Quote End ---

Hi Sean;

Yes I have an overflow on the CVI, how can I determine the value of the buffer in the CVI ?

thx
Rabia
Altera_Forum
Honored Contributor
15 years ago
--- Quote Start ---
Hi,

As pointed out by Sean, the cvi->scaler->vfb->cvo designs may not work because the cvi is overflowing. You can try moving the vfb before the scaler or increase the number of lines of buffering in the cvi.

I still have no idea why the tpg->scaler->vfb->cvo design stops working when adding the scaler. Did you use 1080p or 800x600 in the tpg->vfb->cvo design that works? Please try it with 1080p if you did not already.
--- Quote End ---

Hi vgs;

thank you for reply.
I tried the 1080P with tpg->vfb->cvo. How to define the number of lines buffered in the cvi ?

Rabia
Altera_Forum
Honored Contributor
15 years ago
The number of lines in the cvi is related to your upscale ratio (see Jake's answer above). I think you will be fine if you use (output_height / input_height) + 2 or 3 lines but you really need to give it a try.

I do not think this system can work with the cvi if it does not work with the tpg.
Altera_Forum
Honored Contributor
15 years ago
Hi;

thanks vgs for your reply, it working with cvi->scaler->fb->cvo using 3 buffering lines. I want to add acutally a clipper between the cvi and the scaler. I think that it should work now.

thx
Altera_Forum
Honored Contributor
15 years ago
Hi;
it Doesn't work when I added the clipper, do you think that a frame buffer could resolve the problem ?

thx
Altera_Forum
Honored Contributor
15 years ago
--- Quote Start ---
Hi;
it Doesn't work when I added the clipper, do you think that a frame buffer could resolve the problem ?

thx
--- Quote End ---

Hi,
According to the vip_user guide, the latency of clipper is 0 cycle. So I think it's transparent to CVI and Scaler.
I have a hint for you that when it doesn't work, you may observe that whether an overflow or underflow happened, and try to find out where the dataflow is blocked from that.
By the way, you can use the sinagtap to observe the status signal of each block.
Sean
Altera_Forum
Honored Contributor
15 years ago
Hi;

I verified both ower and underflow, and I have an overflow on the CVI. What can I do ? Can I increase the size of the FIFO in the CVI to avoid that overflow ?

thx
Altera_Forum
Honored Contributor
15 years ago
Hi;

I think that I got everything working with the scaler (with cvi or tpg). When I add a clipper between the cvi and the scaler, I got only result for the tpg. When I use the CVI I got an overflow. I added a frame buffer between the clipper and the scaler and it seems working perfectly. I want to know if there is another method without using the frame buffer because I need the memory for other processing.

thx.
Altera_Forum
Honored Contributor
15 years ago
Hi All,

I'm also having some issues with implementing a scaler video path for upscaling. The following resolutions all at 60Hz are what I'm testing with:

1280x1024 -> 1600x1200 : OK
1024x768 -> 1600x1200 : OK
800x600 -> 1600x1200 : breaks

So for the 800x600 -> 1600x1200 case I can lower the output clock (which is not the correct display clock for this resolution) and get an image out that is not at the right frame rate. This would suggest a throughput issue.

The video path is the following:

CVI -> SCALER -> FB -> CVO

The CVI has 18,000 pixels of FIFO and the Scaler has 12 taps. My guess was 11 x 1600 pixels to be enough CVI FIFO; is it? I read the CVI overflow bit, and it looks OK.

Any suggestions would be very much appreciated.

Thanks,
Mike
Altera_Forum
Honored Contributor
15 years ago
Hello,

I would try setting the Scaler to a simple Bilinear and then if it is working go up step by step from 5 tap to 12 taps (as you need).
What about the Frame buffer is it a double buffer or a triple buffer?

Good luck,

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scaler problem

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