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RTL_FPGAs
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4 years ago

Reed Solomon ii IP core simulation fails to compile in ModelSim

Hello,

I was trying to simulate the Reed Solomon ii DECODER IP provided by Intel with Quartus Pro 20.1, but ran into a compilation issue out of the box. The IP core parameters are configured to generate the Decoder with both Source/Sim generated files chosen to be of VHDL format. I only created the mentor.do file as recommended by Intel and have attached that here (changed extension to .txt in order to upload).

The compilation errors are shown below and appear to be caused by the fact that one of the generated files <rs_new_dec_qprime_altera_rs_ser_dec_191_eq27eva.vhd> instantiating another generated file <altera_avalon_st_splitter.vhd> is missing some input/output ports as can be clearly seen from the Errors.

I'm using ModelSim PE 10.3 Rev 2014.01

# ** Error: rs_new_dec_qprime/altera_rs_ser_dec_191/sim/rs_new_dec_qprime_altera_rs_ser_dec_191_eq27eva.vhd(670): (vcom-1130) Port "in0_empty" of entity "altera_avalon_st_splitter" is not in the component being instantiated.

# ** Error: rs_new_dec_qprime/altera_rs_ser_dec_191/sim/rs_new_dec_qprime_altera_rs_ser_dec_191_eq27eva.vhd(670): (vcom-1130) Port "out0_empty" of entity "altera_avalon_st_splitter" is not in the component being instantiated.

# ** Error: rs_new_dec_qprime/altera_rs_ser_dec_191/sim/rs_new_dec_qprime_altera_rs_ser_dec_191_eq27eva.vhd(670): (vcom-1130) Port "out1_empty" of entity "altera_avalon_st_splitter" is not in the component being instantiated.

# ** Error: rs_new_dec_qprime/altera_rs_ser_dec_191/sim/rs_new_dec_qprime_altera_rs_ser_dec_191_eq27eva.vhd(670): (vcom-1130) Port "out2_empty" of entity "altera_avalon_st_splitter" is not in the component being instantiated.

# ** Error: rs_new_dec_qprime/altera_rs_ser_dec_191/sim/rs_new_dec_qprime_altera_rs_ser_dec_191_eq27eva.vhd(670): (vcom-1130) Port "out3_empty" of entity "altera_avalon_st_splitter" is not in the component being instantiated.

# ** Error: rs_new_dec_qprime/altera_rs_ser_dec_191/sim/rs_new_dec_qprime_altera_rs_ser_dec_191_eq27eva.vhd(670): (vcom-1130) Port "out4_empty" of entity "altera_avalon_st_splitter" is not in the component being instantiated.

# ** Error: rs_new_dec_qprime/altera_rs_ser_dec_191/sim/rs_new_dec_qprime_altera_rs_ser_dec_191_eq27eva.vhd(670): (vcom-1130) Port "out5_empty" of entity "altera_avalon_st_splitter" is not in the component being instantiated.

# ** Error: rs_new_dec_qprime/altera_rs_ser_dec_191/sim/rs_new_dec_qprime_altera_rs_ser_dec_191_eq27eva.vhd(670): (vcom-1130) Port "out6_empty" of entity "altera_avalon_st_splitter" is not in the component being instantiated.

# ** Error: rs_new_dec_qprime/altera_rs_ser_dec_191/sim/rs_new_dec_qprime_altera_rs_ser_dec_191_eq27eva.vhd(670): (vcom-1130) Port "out7_empty" of entity "altera_avalon_st_splitter" is not in the component being instantiated.

# ** Error: rs_new_dec_qprime/altera_rs_ser_dec_191/sim/rs_new_dec_qprime_altera_rs_ser_dec_191_eq27eva.vhd(670): (vcom-1130) Port "out8_empty" of entity "altera_avalon_st_splitter" is not in the component being instantiated.

# ** Error: rs_new_dec_qprime/altera_rs_ser_dec_191/sim/rs_new_dec_qprime_altera_rs_ser_dec_191_eq27eva.vhd(670): (vcom-1130) Port "out9_empty" of entity "altera_avalon_st_splitter" is not in the component being instantiated.

# ** Error: rs_new_dec_qprime/altera_rs_ser_dec_191/sim/rs_new_dec_qprime_altera_rs_ser_dec_191_eq27eva.vhd(670): (vcom-1130) Port "out10_empty" of entity "altera_avalon_st_splitter" is not in the component being instantiated.

# ** Error: rs_new_dec_qprime/altera_rs_ser_dec_191/sim/rs_new_dec_qprime_altera_rs_ser_dec_191_eq27eva.vhd(670): (vcom-1130) Port "out11_empty" of entity "altera_avalon_st_splitter" is not in the component being instantiated.

# ** Error: rs_new_dec_qprime/altera_rs_ser_dec_191/sim/rs_new_dec_qprime_altera_rs_ser_dec_191_eq27eva.vhd(670): (vcom-1130) Port "out12_empty" of entity "altera_avalon_st_splitter" is not in the component being instantiated.

# ** Error: rs_new_dec_qprime/altera_rs_ser_dec_191/sim/rs_new_dec_qprime_altera_rs_ser_dec_191_eq27eva.vhd(670): (vcom-1130) Port "out13_empty" of entity "altera_avalon_st_splitter" is not in the component being instantiated.

# ** Error: rs_new_dec_qprime/altera_rs_ser_dec_191/sim/rs_new_dec_qprime_altera_rs_ser_dec_191_eq27eva.vhd(670): (vcom-1130) Port "out14_empty" of entity "altera_avalon_st_splitter" is not in the component being instantiated.

# ** Error: rs_new_dec_qprime/altera_rs_ser_dec_191/sim/rs_new_dec_qprime_altera_rs_ser_dec_191_eq27eva.vhd(670): (vcom-1130) Port "out15_empty" of entity "altera_avalon_st_splitter" is not in the component being instantiated.

10 Replies

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,


    As I understand it, you have some inquiries related to the Reed Solomon II IP. To facilitate further debugging, just to check with you on the following:

    1. What is the device that you are using?
    2. Just wonder if you have had a chance to try with Modelsim AE?
    3. Are you using Windows or Linux system?
    4. Have you tried with Verilog to see if there is any difference?


    Please let me know if there is any concern. Thank you.


    • RTL_FPGAs's avatar
      RTL_FPGAs
      Icon for New Contributor rankNew Contributor
      4 years ago

      Hello,

      Here are a couple of answers to your questions:

      1. I'm using an Arria-10 device (10AS048E3F29I2SG)
      2. No, I have not tried ModelSim AE
      3. I'm using Windows
      4. I just tried using Verilog, and the simulation did not generate Compilation errors this time. Although I suspect this has more to do with the fact that Verilog is NOT as strict as VHDL when it comes to missing port declarations. The instantiation of the avalon_st_splitter component is identical in the Verilog and VHDL versions of the IP generated.

      Thanks!

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,


    Sorry for the delay. As I understand it, there is no compilation issue when you are using Verilog in the simulation. Just to check if you are able to use this as workaround to proceed?


    Please let me know if there is any concern. Thank you.


    • RTL_FPGAs's avatar
      RTL_FPGAs
      Icon for New Contributor rankNew Contributor
      4 years ago

      Yes, the workaround does unstick us not making progress in our work, but I'm hoping that Intel is still planning to look into and fix the compilation issue using VHDL? Prior to writing this message on this forum, we spent more than just a handful of hours trying to figure out what we could possibly be doing wrong.

      At the very least this should be documented and listed as a limitation for the IP if Intel does not plan to address/fix the VHDL model compilation issue. Can you confirm?

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,


    Thanks for your update. Glad to hear that the workaround is helpful to un-gate your progress.


    Would you mind to share with me a simple simulation example which could replicate your observation together with detailed steps to run it in Modelsim? This would be helpful for me to feedback to factory for future enhancement.


    Thank you.


    • RTL_FPGAs's avatar
      RTL_FPGAs
      Icon for New Contributor rankNew Contributor
      4 years ago

      The simulation files are generated for VHDL (instead of Verilog) when setting up the core (the core parameters themselves shouldn't matter).

      You can then run the script I attached above (which is just the script provided by Intel with the variables set for my environment). The errors will appear following this step. Nothing more special needs to be run or separate TB required to see the failure.

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,


    Just to keep you posted on my latest findings. I am able to replicate this error by simulating the default VHDL sim files generated by the IP. There seems to be no issue when I tested with Q19.4Pro. The issue seems to start with Q20.1Pro. I will file a case to Engineering reporting this for future fix.


    Thank you.


    • RTL_FPGAs's avatar
      RTL_FPGAs
      Icon for New Contributor rankNew Contributor
      4 years ago

      Glad you could easily replicate it on your end. Thanks for keeping me posted.

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,


    Thanks for your update. For your information, I have file a case to Engineering for fix in future Quartus release. I will continue to follow up them offline on this. Sorry for all the inconvenience.


  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,


    I believe the initial inquiry has been addressed. I will continue to follow up with Engineering offline. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.