Forum Discussion

RTL_FPGAs's avatar
RTL_FPGAs
Icon for New Contributor rankNew Contributor
4 years ago

Reed Solomon ii IP core simulation fails to compile in ModelSim

Hello, I was trying to simulate the Reed Solomon ii DECODER IP provided by Intel with Quartus Pro 20.1, but ran into a compilation issue out of the box. The IP core parameters are configured to gen...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


Just to keep you posted on my latest findings. I am able to replicate this error by simulating the default VHDL sim files generated by the IP. There seems to be no issue when I tested with Q19.4Pro. The issue seems to start with Q20.1Pro. I will file a case to Engineering reporting this for future fix.


Thank you.


RTL_FPGAs's avatar
RTL_FPGAs
Icon for New Contributor rankNew Contributor
4 years ago

Glad you could easily replicate it on your end. Thanks for keeping me posted.