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RTL_FPGAs's avatar
RTL_FPGAs
Icon for New Contributor rankNew Contributor
4 years ago

Reed Solomon ii IP core simulation fails to compile in ModelSim

Hello, I was trying to simulate the Reed Solomon ii DECODER IP provided by Intel with Quartus Pro 20.1, but ran into a compilation issue out of the box. The IP core parameters are configured to gen...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


As I understand it, you have some inquiries related to the Reed Solomon II IP. To facilitate further debugging, just to check with you on the following:

  1. What is the device that you are using?
  2. Just wonder if you have had a chance to try with Modelsim AE?
  3. Are you using Windows or Linux system?
  4. Have you tried with Verilog to see if there is any difference?


Please let me know if there is any concern. Thank you.


  • RTL_FPGAs's avatar
    RTL_FPGAs
    Icon for New Contributor rankNew Contributor
    4 years ago

    Hello,

    Here are a couple of answers to your questions:

    1. I'm using an Arria-10 device (10AS048E3F29I2SG)
    2. No, I have not tried ModelSim AE
    3. I'm using Windows
    4. I just tried using Verilog, and the simulation did not generate Compilation errors this time. Although I suspect this has more to do with the fact that Verilog is NOT as strict as VHDL when it comes to missing port declarations. The instantiation of the avalon_st_splitter component is identical in the Verilog and VHDL versions of the IP generated.

    Thanks!