New Contributor
Regular ContributorHi,
Thanks for your update. Glad to hear that the workaround is helpful to un-gate your progress.
Would you mind to share with me a simple simulation example which could replicate your observation together with detailed steps to run it in Modelsim? This would be helpful for me to feedback to factory for future enhancement.
Thank you.
New ContributorThe simulation files are generated for VHDL (instead of Verilog) when setting up the core (the core parameters themselves shouldn't matter).
You can then run the script I attached above (which is just the script provided by Intel with the variables set for my environment). The errors will appear following this step. Nothing more special needs to be run or separate TB required to see the failure.
