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RTL_FPGAs's avatar
RTL_FPGAs
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4 years ago

Reed Solomon ii IP core simulation fails to compile in ModelSim

Hello, I was trying to simulate the Reed Solomon ii DECODER IP provided by Intel with Quartus Pro 20.1, but ran into a compilation issue out of the box. The IP core parameters are configured to gen...
CheepinC_altera's avatar
CheepinC_altera
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4 years ago

Hi,


Sorry for the delay. As I understand it, there is no compilation issue when you are using Verilog in the simulation. Just to check if you are able to use this as workaround to proceed?


Please let me know if there is any concern. Thank you.


  • RTL_FPGAs's avatar
    RTL_FPGAs
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    4 years ago

    Yes, the workaround does unstick us not making progress in our work, but I'm hoping that Intel is still planning to look into and fix the compilation issue using VHDL? Prior to writing this message on this forum, we spent more than just a handful of hours trying to figure out what we could possibly be doing wrong.

    At the very least this should be documented and listed as a limitation for the IP if Intel does not plan to address/fix the VHDL model compilation issue. Can you confirm?