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RTL_FPGAs's avatar
RTL_FPGAs
Icon for New Contributor rankNew Contributor
5 years ago

Reed Solomon ii IP core simulation fails to compile in ModelSim

Hello, I was trying to simulate the Reed Solomon ii DECODER IP provided by Intel with Quartus Pro 20.1, but ran into a compilation issue out of the box. The IP core parameters are configured to gen...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


Sorry for the delay. As I understand it, there is no compilation issue when you are using Verilog in the simulation. Just to check if you are able to use this as workaround to proceed?


Please let me know if there is any concern. Thank you.