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Altera_Forum
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17 years ago

Problem with DDR SDRAM controller (words swapped)

I'm using version 8.0 of the Altera DDR SDRAM controller to interface to a Micron MT46V16M16BG-6 SDRAM. The control signals between my local controller and the Altera DDR SDRAM block look fine when I examine them using signaltap, and match those in the datasheet, but the data I'm reading back is shifted relative to the input.

For example, I perform a 4x burst write by applying the following data to the local_wdata[31..0] port:

00000000h, 00010001h, 00020002h, 00030003h

But the following data is returned on the local_rdata[31..0] port:

00000840h, 00010000h, 00020001h, 00030002h

The SRAM chip has a 16 bit wide data interface so it appears that the data is offset by one clock somewhere. I've checked that the settings in the contraints tab matches the DQ/DQS pins I've used, but even if I change them it doesn't make any difference to the behaviour. I have checked the pin settings against the board, and checked the timing settings against those listed in the datasheet numerous times. I'm using my own PLL block but I've checked that the frequencies and phases match those of the example PLL generated by the Megacore. I've tried inverting clocks etc but nothing seems to work. Can anyone shed any more light on this problem?

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Does it work with the example driver and the PLL generated by the Megacore?

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Helo,

    I have met the same problem also with PLL megacore, in my opinion, it seems that data arrive capture registers later than shifted phase DQS, but I do not know how to modifier clock delay control on Cyclone 2 so that I can delay DQS more.

    Can anyone show me how to change phase shift DQS, pleaseeee!

    Thanks in advance.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Have you entered board trace models into Quartus? You may have a lot of skew which quartus could correct.

    What have you set the Address/Command phase to in the megawizard.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi,

    Finally I solved problem, the problem is data come later than DQS, so DQS got the wrong order data group. Thus, we have to modified "Clock delay control circuitry" to delay DQS, I find no where show me how to modify it in Cyclone2. Actually, after Megacore generating ddr2 controller, look into file "ddr2_sdram_component_classic_0_auk_ddr_dqs_group.v" in my project directory, we can change Clock delay control circuitry by modify this line:

    defparam dqs_delay_ctrl.delay_chain = "61",

    dqs_delay_ctrl.delay_chain_mode = "static",

    dqs_delay_ctrl.lpm_type = "cycloneii_clk_delay_ctrl";

    We have 0-63 delay degrees, with 63 is the largest. By default, megacore will set it to 18.

    Then we have consider about resync_clock, by turn on Manual Timing in Megacore wizard, then change Resync. clock is 4, phase is 90 (in this case because the data come late, if the data come sooner, we have to shift back), ignore error messages.

    Then generating the system, after that, change Clock delay control circuitry like above, then compile project. After compilation, look on the timing report for DDR2, if setup slack for DQ is negative then we have to change clock delay and recompile. If setup slack is positive then we look at setup slack for resynchronize data, if it is large negative, then return to megacore wizard change phase shift for resync clock...It looks like that and it ran...

    Info:

    Info: DDR read data capture: DDR Data to DQS strobe edges at capture registers.

    Info: Setup slack is 289 ps associated with pin 'ddr2_dq[7]' ( variation port 'dq(15)', 'input_cell_H[0]')

    Info: Hold slack is 2777 ps associated with pin 'ddr2_dq[1]' ( variation port 'dq(1)', 'input_cell_H[0]')

    Info:

    Info: Read data resynchronisation: Captured data to resync clock at resync registers ('resynched_data').

    Warning: Setup slack is -1919 ps associated with pin 'ddr2_dq[1]' ( variation port 'dq(1)', 'input_cell_H[0]') ( Total of 32 paths with negative slack)

    Info: Hold slack is 1989 ps associated with pin 'ddr2_dq[0]' ( variation port 'dq(8)', 'input_cell_H[0]')