Problem with DDR SDRAM controller (words swapped)

Hi,

Finally I solved problem, the problem is data come later than DQS, so DQS got the wrong order data group. Thus, we have to modified "Clock delay control circuitry" to delay DQS, I find no where show me how to modify it in Cyclone2. Actually, after Megacore generating ddr2 controller, look into file "ddr2_sdram_component_classic_0_auk_ddr_dqs_group.v" in my project directory, we can change Clock delay control circuitry by modify this line:

defparam dqs_delay_ctrl.delay_chain = "61",

dqs_delay_ctrl.delay_chain_mode = "static",

dqs_delay_ctrl.lpm_type = "cycloneii_clk_delay_ctrl";

We have 0-63 delay degrees, with 63 is the largest. By default, megacore will set it to 18.

Then we have consider about resync_clock, by turn on Manual Timing in Megacore wizard, then change Resync. clock is 4, phase is 90 (in this case because the data come late, if the data come sooner, we have to shift back), ignore error messages.

Then generating the system, after that, change Clock delay control circuitry like above, then compile project. After compilation, look on the timing report for DDR2, if setup slack for DQ is negative then we have to change clock delay and recompile. If setup slack is positive then we look at setup slack for resynchronize data, if it is large negative, then return to megacore wizard change phase shift for resync clock...It looks like that and it ran...

Info:

Info: DDR read data capture: DDR Data to DQS strobe edges at capture registers.

Info: Setup slack is 289 ps associated with pin 'ddr2_dq[7]' ( variation port 'dq(15)', 'input_cell_H[0]')

Info: Hold slack is 2777 ps associated with pin 'ddr2_dq[1]' ( variation port 'dq(1)', 'input_cell_H[0]')

Info:

Info: Read data resynchronisation: Captured data to resync clock at resync registers ('resynched_data').

Warning: Setup slack is -1919 ps associated with pin 'ddr2_dq[1]' ( variation port 'dq(1)', 'input_cell_H[0]') ( Total of 32 paths with negative slack)

Info: Hold slack is 1989 ps associated with pin 'ddr2_dq[0]' ( variation port 'dq(8)', 'input_cell_H[0]')