Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorProblem with DDR SDRAM controller (words swapped)
I'm using version 8.0 of the Altera DDR SDRAM controller to interface to a Micron MT46V16M16BG-6 SDRAM. The control signals between my local controller and the Altera DDR SDRAM block look fine when I...
Altera_ForumHonored Contributor
Honored ContributorHelo,
I have met the same problem also with PLL megacore, in my opinion, it seems that data arrive capture registers later than shifted phase DQS, but I do not know how to modifier clock delay control on Cyclone 2 so that I can delay DQS more. Can anyone show me how to change phase shift DQS, pleaseeee! Thanks in advance.
