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Altera_Forum
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17 years ago

Problem with DDR SDRAM controller (words swapped)

I'm using version 8.0 of the Altera DDR SDRAM controller to interface to a Micron MT46V16M16BG-6 SDRAM. The control signals between my local controller and the Altera DDR SDRAM block look fine when I...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Helo,

I have met the same problem also with PLL megacore, in my opinion, it seems that data arrive capture registers later than shifted phase DQS, but I do not know how to modifier clock delay control on Cyclone 2 so that I can delay DQS more.

Can anyone show me how to change phase shift DQS, pleaseeee!

Thanks in advance.