Pre-Emphasis with IIR Filter

I just modelled your equation in Matlab :

x = ;  %impulse input
k = .95;
 
y(1)=0;
for i = 2:1000
   y(i)=x(i)-(x(i-1)*k);
end
 
fx = fftshift(fft(x));
fy = fftshift(fft(y));
plot(abs(fx));hold
plot(abs(fy),'r')

However I must admit that if I enter:

It is to do with my first assumption about y(1) = 0

here is my first go:

elsif (clk'event AND clk = '1') then
 
X <= Input;
Yn_tmp := Xi1 * b0_var;
Yn_tmp2 := Yn_tmp / div;
Yn := resize(Xi, Yn_tmp2'length) - Yn_tmp2;
 
Output <= resize(Yn, Output'length);
Xi1 := resize(Yn, Xi1'length); 
Xi := X; 
 
end if;
 

OK....Thank You Kaz for your quick reply!

I tried this code and I think the pre-emphasis works. But the output-signal is very distorted in the higher frequencies and the lower frequencies are very attenuated. Here is the modified VHDL-code:

Frequencies below to Om=1.0644 rads are attenuated, so, frequencies above to Om=1.0644 rads are amplified almost two times for ones near to pi. Check you are using an enough bit size for output, a small one could cause your problem.

Hi,

If you are processing audio or speech, perhaps DC component is missing, it doesn't carry information. Direct implementation of pre-emphasis filter without DC unity gain normalization , implies just a 1 bit growth on output word size at highest frequency (pi).

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity preemphasis is
generic (
--Word size
N: integer:=8;
--Fractional bits
M: integer:=7;
--h for preemphasis filter
h1: real:= 0.97
);
port (
--Input
xn: in std_logic_vector(N-1 downto 0);
--Output
yn: out std_logic_vector(N downto 0);
--Clock
clk: in std_logic;
--Reset
reset_n: in std_logic
);
end entity;
architecture rtl of preemphasis is
signal xn1: std_logic_vector(N-1 downto 0);
signal mult_out: std_logic_vector(2*N-1 downto 0);
signal coeff: std_logic_vector(N-1 downto 0);
signal ynreg,sub_out: std_logic_vector(N downto 0);
begin
--Wired coeff h
coeff<=std_logic_vector(to_signed(integer(round(h1*real(2**M))),N));
--Registers for x and y
process(xn,clk,reset_n)
begin
if(reset_n='0') then
xn1<=(others=>'0');
ynreg<=(others=>'0');
elsif(rising_edge(clk)) then
xn1<=xn;
ynreg<=sub_out;
end if;
end process;
--Multiplier
mult_out<=std_logic_vector(signed(xn1)*signed(coeff));
--Substract with sign extend
sub_out<=std_logic_vector(signed(xn(N-1)&xn)-signed(mult_out(M+N downto M)));
--Connects register to output
yn<=ynreg;
end architecture;

Hello!

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL; 
entity PREemphase is
    
    
    Port (     
            Input           : in  signed (13 downto 0);
            Output         : out signed (14 downto 0);
            CLK              : in  STD_LOGIC;
            RST             : in  STD_LOGIC
         );
            
    end PREemphase;
            
architecture verhalten of PREemphase is
--signal X     : signed (13 downto 0);
signal Xi    : signed (13 downto 0);
signal Xi1   : signed (13 downto 0);
begin
    filter: process(RST, CLK)
    --variable Xi         : signed (13 downto 0); 
    variable Yn         : signed (21 downto 0); 
    --variable Xi1         : signed (20 downto 0); 
    variable Yn_tmp     : signed (21 downto 0); 
    variable Yn_tmp2     : signed (21 downto 0); 
    variable b0_var     : signed ( 7 downto 0); 
    variable div        : signed ( 7 downto 0); 
    
    begin
        if (RST = '0') then
            --Xi    := (others => '0');
            --Xi1     := (others => '0');
            Yn_tmp     := (others => '0');
            Yn_tmp2    := (others => '0');
            b0_var     := ("01100001"); --97
            div        := ("01100100"); --100
            Yn        := (others => '0');
            
            
        elsif (clk'event AND clk = '1') then
            --X <= Input;
            Xi             <= Input; --new value
            Yn_tmp     := Xi1 * b0_var;
            Yn_tmp2    := Yn_tmp / div;
            Yn            := resize(Xi, Yn'length) - Yn_tmp2;
            
            Output       <= resize(Yn, Output'length);
            Xi1            <= Xi; --old value
            
        end if;
    end process;            
    
end verhalten;