Pre-Emphasis with IIR Filter

If you are processing audio or speech, perhaps DC component is missing, it doesn't carry information. Direct implementation of pre-emphasis filter without DC unity gain normalization , implies just a 1 bit growth on output word size at highest frequency (pi).

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity preemphasis is
generic (
--Word size
N: integer:=8;
--Fractional bits
M: integer:=7;
--h for preemphasis filter
h1: real:= 0.97
);
port (
--Input
xn: in std_logic_vector(N-1 downto 0);
--Output
yn: out std_logic_vector(N downto 0);
--Clock
clk: in std_logic;
--Reset
reset_n: in std_logic
);
end entity;
architecture rtl of preemphasis is
signal xn1: std_logic_vector(N-1 downto 0);
signal mult_out: std_logic_vector(2*N-1 downto 0);
signal coeff: std_logic_vector(N-1 downto 0);
signal ynreg,sub_out: std_logic_vector(N downto 0);
begin
--Wired coeff h
coeff<=std_logic_vector(to_signed(integer(round(h1*real(2**M))),N));
--Registers for x and y
process(xn,clk,reset_n)
begin
if(reset_n='0') then
xn1<=(others=>'0');
ynreg<=(others=>'0');
elsif(rising_edge(clk)) then
xn1<=xn;
ynreg<=sub_out;
end if;
end process;
--Multiplier
mult_out<=std_logic_vector(signed(xn1)*signed(coeff));
--Substract with sign extend
sub_out<=std_logic_vector(signed(xn(N-1)&xn)-signed(mult_out(M+N downto M)));
--Connects register to output
yn<=ynreg;
end architecture;