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Altera_Forum
Honored Contributor
16 years agoHello!
this is my new version. i tried to solve the problem with the assignments.library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity PREemphase is
Port (
Input : in signed (13 downto 0);
Output : out signed (14 downto 0);
CLK : in STD_LOGIC;
RST : in STD_LOGIC
);
end PREemphase;
architecture verhalten of PREemphase is
--signal X : signed (13 downto 0);
signal Xi : signed (13 downto 0);
signal Xi1 : signed (13 downto 0);
begin
filter: process(RST, CLK)
--variable Xi : signed (13 downto 0);
variable Yn : signed (21 downto 0);
--variable Xi1 : signed (20 downto 0);
variable Yn_tmp : signed (21 downto 0);
variable Yn_tmp2 : signed (21 downto 0);
variable b0_var : signed ( 7 downto 0);
variable div : signed ( 7 downto 0);
begin
if (RST = '0') then
--Xi := (others => '0');
--Xi1 := (others => '0');
Yn_tmp := (others => '0');
Yn_tmp2 := (others => '0');
b0_var := ("01100001"); --97
div := ("01100100"); --100
Yn := (others => '0');
elsif (clk'event AND clk = '1') then
--X <= Input;
Xi <= Input; --new value
Yn_tmp := Xi1 * b0_var;
Yn_tmp2 := Yn_tmp / div;
Yn := resize(Xi, Yn'length) - Yn_tmp2;
Output <= resize(Yn, Output'length);
Xi1 <= Xi; --old value
end if;
end process;
end verhalten;I fixed the output, so that it has one more bit. The higher frequencies are ok now, but the lower frequencies are still very attenuated. For example a signal f=100Hz nearly disappears after the filter. The thing is that normally the frequencies below 3.18 kHz have to go through without any increase oder decrease. @parrado: Thank you for the code. I will check it out!!